Frédéric Blanc » Hyperproto_FPGA

h1. APPSFPGA

h2. VHDL CODE

*appsfpga_io_a.vhd*

This is the architecture for the appsfpga_io module, which creates

all clocks for the project and instantiates all necessary clock

and output buffers. It also reads the dip switch inputs and

passes those values back to the top level.

*ddr_lvds_io_ea.vhd*

This is the architecture and entity for module ddr_lvds_io. This module maps

an 4 input values to an value through a 4 to 1 OSERDES and outputs a lvds pair

*ddr_se_io_ea.vhd*

This is the architecture and entity for module ddr_se_io. This module maps

an 4 input values to an value through a 4 to 1 OSERDES

*appcore_a.vhd*

This is the architecture for module appcore, which simply

instantiates the level 2 modules pgen and cnts.

*pgen_a.vhd*

This is the architecture for module pgen, which produces all the

data and control signals sent to the dmd controller. It creates

these signals using the counters in module cnts and by muxing

signals created by pgs, pgd, and pgg. This allows the user to

choose either single block phased reset, dual block phased reset,

or global reset.

*pgen_clear_a.vhd*

This is the architecture for the module pgen_pgc, which will

create signals unique to operation in the single block phased

reset mode including row valid, row mode, block mode, block

address, and data valid.

*pgen_pgs_a.vhd*

This is the architecture for the module pgen_pgs, which will

create signals unique to operation in the single block phased

reset mode including row valid, row mode, block mode, block

address, and data valid.

*pgen_pgd_a.vhd*

This is the architecture for the module pgen_pgd, which will

create signals unique to operation in the dual block phased

reset mode including row valid, row mode, block mode, block

address, and data valid.

*pgen_pgg_a.vhd*

This is the architecture for module pgen_pgg, which creates

signals unique to operation in the global reset mode including

row valid, row mode, block mode, block address, and data valid.

*pgen_pgq_a.vhd*

This is the architecture for the module pgen_pgq, which will

create signals unique to operation in the quad block phased

reset mode including row valid, row mode, block mode, block

address, and data valid.

*cnts_a.vhd*

This is the architecture for module cnts, which contains all

counters needed to control timing of output signals.