Wiki DLP4100

Overview¶

The DLP® Discovery™ 4100 (D4100) is the latest in a series of spatial light modulation development kits from Texas
Instruments. Users of the D4100 Starter Kit have the ability to manipulate visible, ultraviolet and near-infrared light
with extremely high performance and high resolution.
The D4100 offers developers a flexible platform to design products to fit most any application using the proven
reliability of DLP technology.

Fig 1: System Overview

New version 2017	Actual	Name
DLPC410	DDC4100 (FPGA X5VLX30)	Digital Controller for Discovery 4100 chipset
DLPR410	XCF16	PROM for Discovery 4100 chipset
DLPA200	DAD2000	DMD Micromirror Driver

Configuration Jumpers¶

Fig 2: D4100 Controller Configuration Jumpers and LED

LED1 - USB status
CY7C68013A_128
LED2 - APPSFPGA status
(FPGA PIN N14)

LED	Status
RED	BAD
GREEN	OK

LED3 - DDC4000 status

LED	Status
RED	BAD
GREEN	OK

LED9..12 - LED status
LED9 - DDC_LED0 Status LED for the DDC4000
The LED0 signal is typically connected
to an LED to show that the DLPC410
is operating normally.
The signal is 1 Hz with 50% duty cycle,
otherwise known as the heartbeat
LED10 - DDC_LED1 Status LED for the DDC4000
The LED1 signal is typically connected to an LED
indicator to show the status of system initialization
and the status of the clock circuits. The LED1 signal
is asserted only when system initialization is
complete and clock circuits are initialized. Logically,
these signals are ANDed together to show an indication
of the health of the system. If the Phase Locked
Loop (PLL) connected to the data clock and the DMD
clock are functioning correctly after system
initialization, the LED will be illuminated
LED11 - VLED0 This logic is to be defined by the APPSFPGA application. Drive low to turn on the led. Drive high to
turn off the led(FPGA PIN AK19).
LED12 - VLED1 This logic is to be defined by the APPSFPGA application. Drive low to turn on the led. Drive high to
turn off the led(FPGA PIN AJ19).

J2 – EXP Voltage Select

J4 – Used to select the revision of firmware loaded from the PROM to the APPSFPGA.

Jumper Position	Revision Version
open	0
close	1

J5 – Shared USB signal disabled

Jumper Position	USB Signals
0-1	Disconnected from FPGA
1-2	Connected to FPGA
2-3	Automatically connect USB signals to FPGA when USB is connected to host PC

J7 – USB EEPROM Programming Header

Used to temporally disconnect the USB EEPROM fromthe device so the device can load its internal
boot loader rather than any code in the EEPROM. Install J8 for Cypress internal boot loader.

J10 – DAD2000 B Output Enable

Used to enable the outputs for DAD2000 B. This needs to be enabled only if using the 1080p DMD,
otherwise this can be disabled.

Jumper Position	DAD2000 B Outputs
open	Disabled
close	Enabled

J11 – Used to select the revision of firmware loaded from the PROM to the DDC4100 (FPGA X5VLX30).

Jumper Position	Revision Version
open	0
close	1

SW1 - Dipswitches

Functionality defined by APPSFPGA programming. In default test pattern code:

_Switch Number	_Effect
1	ON = float – float all mirrors
2	ON = counter halt – stop counter, this will freeze the image on the DMD
3	ON = complement data – causes DDC 4000 to complement all data it receives
4	ON = north/south flip – causes the DDC 4000 to reverse order of row loading, effectively flipping the image
6	Dictates the type of reset being used MSB ON = 1
5	Dictates the type of reset being used LSB ON = 1
	00 : single block phased reset
	01 : dual block phased reset
	10 : global reset
	11 : quad block phased reset
7	ON = Row Address Mode
8	ON = WDT Enable, disables other resets

SW2 - Push Button Momentary Switch

Functionality defined by APPSFPGA. This switch is used for APPS_LOGIC_RESET in the default code.

SW3 - Push Button Momentary Switch

Functionality defined by APPSFPGA. This switch is used for APPS_LOGIC_MIRROR_FLOAT in the default code.

SW4 - POWER STANDBY