Xilink Vivado » History » Version 89
Frédéric Blanc, 2023-12-04 15:21
1 | 1 | Frédéric Blanc | h1. Xilink Vivado |
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2 | 89 | Frédéric Blanc | {{toc}} |
3 | 1 | Frédéric Blanc | h2. installation Ubuntu 20.04 |
4 | 33 | Frédéric Blanc | |
5 | sur le site de xilinx telecharger: |
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6 | https://www.xilinx.com/support/download.html |
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7 | 35 | Frédéric Blanc | Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer |
8 | 33 | Frédéric Blanc | |
9 | 37 | Frédéric Blanc | |
10 | 34 | Frédéric Blanc | *en root* |
11 | 33 | Frédéric Blanc | |
12 | 1 | Frédéric Blanc | <pre><code class="shell"> |
13 | 42 | Frédéric Blanc | sudo bash |
14 | 40 | Frédéric Blanc | export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr |
15 | 39 | Frédéric Blanc | chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
16 | 36 | Frédéric Blanc | sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
17 | 33 | Frédéric Blanc | </code></pre> |
18 | 41 | Frédéric Blanc | echo $XILINXD_LICENSE_FILE |
19 | 2100@flexalter.laas.fr |
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20 | 33 | Frédéric Blanc | |
21 | 32 | Frédéric Blanc | |
22 | https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/ |
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23 | |||
24 | 1 | Frédéric Blanc | h2. installation Windows |
25 | |||
26 | 6 | Frédéric Blanc | |
27 | 5 | Frédéric Blanc | h3. Vivado 2022.2 |
28 | |||
29 | 2 | Frédéric Blanc | Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory |
30 | |||
31 | On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. |
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32 | 3 | Frédéric Blanc | |
33 | <pre><code class="shell"> |
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34 | dir D:\Public\RedPitaya-FPGA |
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35 | vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 |
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36 | </code></pre> |
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37 | 4 | Frédéric Blanc | |
38 | !clipboard-202304201305-exdsl.png! |
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39 | 5 | Frédéric Blanc | |
40 | We recommend Vivado 2020.1 |
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41 | 7 | Frédéric Blanc | |
42 | 8 | Frédéric Blanc | h3. Vivado 2020.1 |
43 | 7 | Frédéric Blanc | |
44 | 22 | Frédéric Blanc | h2. Création d'un nouveau projet |
45 | |||
46 | 47 | Frédéric Blanc | Create a new project with Vivado. |
47 | !clipboard-202306070934-1ikrj.png! |
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48 | |||
49 | 67 | Frédéric Blanc | *Select the device xc7z010clg400-1* |
50 | 47 | Frédéric Blanc | |
51 | Add the constraint redpitaya.xdc . |
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52 | |||
53 | Create a new Block Design |
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54 | !clipboard-202306070939-6delu.png! |
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55 | |||
56 | 57 | Frédéric Blanc | *ERROR: Could not find a top module* |
57 | |||
58 | solution Create an HDL Wrapper. |
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59 | !clipboard-202306201313-n0s0q.png! |
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60 | |||
61 | 47 | Frédéric Blanc | h3. source |
62 | |||
63 | 86 | Frédéric Blanc | source: https://github.com/lvillasen/RedPitaya-Hello-World |
64 | 24 | Frédéric Blanc | |
65 | Clone the repositiry |
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66 | |||
67 | Create a new project with Vivado. |
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68 | 47 | Frédéric Blanc | !clipboard-202306070934-1ikrj.png! |
69 | 24 | Frédéric Blanc | |
70 | 66 | Frédéric Blanc | *Select the device xc7z010clg400-1* |
71 | 1 | Frédéric Blanc | |
72 | 47 | Frédéric Blanc | Add the constraint redpitaya.xdc . |
73 | 1 | Frédéric Blanc | |
74 | 47 | Frédéric Blanc | Create a new Block Design |
75 | !clipboard-202306070939-6delu.png! |
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76 | 24 | Frédéric Blanc | |
77 | Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options. |
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78 | |||
79 | Add Module counter.v from the menu. |
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80 | |||
81 | clic doit |
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82 | !clipboard-202304261446-zpxnx.png! |
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83 | |||
84 | Add a Binary Counter from thr Add IP menu. |
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85 | |||
86 | Add a port called led_o with components from 7 down to 0. |
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87 | |||
88 | !clipboard-202304261452-qlhno.png! |
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89 | |||
90 | 25 | Frédéric Blanc | connect |
91 | |||
92 | 28 | Frédéric Blanc | !clipboard-202304261515-hhbvn.png! |
93 | 25 | Frédéric Blanc | |
94 | 24 | Frédéric Blanc | From the menu click on Validate Design |
95 | |||
96 | In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper' |
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97 | |||
98 | 26 | Frédéric Blanc | !clipboard-202304261503-3iuu2.png! |
99 | |||
100 | 24 | Frédéric Blanc | Proceed to run Synthesis, Implementation and Bitstream Generation |
101 | |||
102 | Find the bitstream file (you may use the command 'find . -name *bit') |
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103 | |||
104 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
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105 | |||
106 | 22 | Frédéric Blanc | clic doit |
107 | 23 | Frédéric Blanc | !clipboard-202304261446-zpxnx.png! |
108 | 22 | Frédéric Blanc | |
109 | 10 | Frédéric Blanc | Tcl Console |
110 | |||
111 | 9 | Frédéric Blanc | <pre><code class="shell"> |
112 | cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink |
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113 | source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl |
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114 | </code></pre> |
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115 | |||
116 | 11 | Frédéric Blanc | !clipboard-202304251008-te1ah.png! |
117 | 17 | Frédéric Blanc | pour éviter cette erreur copier le dossier core dans ../tmp/ |
118 | 11 | Frédéric Blanc | |
119 | 16 | Frédéric Blanc | attachment:cores.zip |
120 | 12 | Frédéric Blanc | |
121 | 18 | Frédéric Blanc | h4. Bitstream |
122 | |||
123 | 43 | Frédéric Blanc | le Bitstream ce trouve dans le dossier /.../RedPitaya/fpga/<project...>/<project...>.runs/impl_1 |
124 | |||
125 | 18 | Frédéric Blanc | !clipboard-202304251107-19zhk.png! |
126 | |||
127 | 20 | Frédéric Blanc | |
128 | le fichier bitstream doit être remplacer le fichier /dev/xdevcfg |
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129 | |||
130 | 44 | Frédéric Blanc | |
131 | *rp-ip 140.93.64.197* |
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132 | |||
133 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
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134 | |||
135 | Connect to the RedPitaya (ssh root@rp-ip) |
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136 | |||
137 | 88 | Frédéric Blanc | Program the FPGA with the command: |
138 | *cat file_name.bit > /dev/xdevcfg* |
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139 | 44 | Frédéric Blanc | |
140 | 69 | Frédéric Blanc | h2. GPIO |
141 | |||
142 | |||
143 | 45 | Frédéric Blanc | h3. Console TCL |
144 | 44 | Frédéric Blanc | |
145 | 45 | Frédéric Blanc | utilisation des exemples |
146 | |||
147 | https://github.com/RedPitaya/RedPitaya-FPGA |
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148 | |||
149 | !clipboard-202306021352-vc13m.png! |
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150 | |||
151 | utiliser les commandes suivante dans vivado console TCL |
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152 | |||
153 | <pre><code class="shell"> |
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154 | cd /tools/redpitaya/RedPitaya-FPGA-master/prj/Examples |
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155 | source make_project.tcl |
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156 | </code></pre> |
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157 | 46 | Frédéric Blanc | cela va ouvrir le projet complet de Led_Blink |
158 | |||
159 | 48 | Frédéric Blanc | h3. GPIO |
160 | |||
161 | 50 | Frédéric Blanc | !clipboard-202306071537-n2vfw.png! |
162 | 49 | Frédéric Blanc | connecteur E1 |
163 | 65 | Frédéric Blanc | exp_n_tri_io (OUT) |
164 | exp_p_tri_io (IN) |
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165 | 51 | Frédéric Blanc | |
166 | 52 | Frédéric Blanc | exp_n_tri_io[1.1] correspond a DIO1_N |
167 | 53 | Frédéric Blanc | !clipboard-202306081407-xqky7.png! |
168 | !clipboard-202306081409-vulz6.png! |
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169 | 54 | Frédéric Blanc | exemple de slice pour extraire du vecteur exp_p_tri_io[7.0] le scalaire exp_p_tri_io[3.3] qui correspond au GPIO DIO3_P du connecteur E1 |
170 | 53 | Frédéric Blanc | Slice pour démultiplexer le vecteur |
171 | Concat pour multiplexer |
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172 | 48 | Frédéric Blanc | |
173 | 70 | Frédéric Blanc | h4. bidirectional |
174 | |||
175 | 72 | Frédéric Blanc | h5. IOBUF |
176 | 70 | Frédéric Blanc | |
177 | !clipboard-202310231532-idfoo.png! |
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178 | |||
179 | https://docs.xilinx.com/r/en-US/ug1344-versal-architecture-libraries/IBUFDS_DIFF_OUT_IBUFDISABLE |
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180 | |||
181 | 72 | Frédéric Blanc | h5. Utility Buffer (seulement pour les horloges) |
182 | 1 | Frédéric Blanc | |
183 | https://www.xilinx.com/products/intellectual-property/util_ds_buf.html#documentation |
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184 | 72 | Frédéric Blanc | |
185 | h5. Modification du fichier de contraite |
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186 | 71 | Frédéric Blanc | |
187 | 73 | Frédéric Blanc | <pre><code class="shell"> |
188 | ### set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}] |
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189 | set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}] |
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190 | ### IN |
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191 | set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_in7[*]}] |
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192 | set_property SLEW FAST [get_ports {exp_p_in7[*]}] |
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193 | set_property DRIVE 8 [get_ports {exp_p_in7[*]}] |
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194 | set_property PULLTYPE PULLUP [get_ports {exp_p_in7[*]}] |
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195 | set_property PACKAGE_PIN M14 [get_ports {exp_p_in7[0]}] |
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196 | </code></pre> |
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197 | |||
198 | |||
199 | |||
200 | 55 | Frédéric Blanc | h3. FIFO |
201 | |||
202 | 59 | Frédéric Blanc | !clipboard-202306221115-rthjy.png! |
203 | 55 | Frédéric Blanc | IP FIFO generator |
204 | 58 | Frédéric Blanc | *IN* |
205 | 1 | Frédéric Blanc | !clipboard-202306151112-equbx.png! |
206 | 58 | Frédéric Blanc | *OUT* |
207 | 56 | Frédéric Blanc | !clipboard-202306151112-gvamj.png! |
208 | |||
209 | 62 | Frédéric Blanc | h3. Shift Register |
210 | |||
211 | !clipboard-202307041436-0ex9q.png! |
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212 | |||
213 | 63 | Frédéric Blanc | h3. Block Memory Generator |
214 | |||
215 | !clipboard-202307041437-3fhkj.png! |
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216 | |||
217 | 75 | Frédéric Blanc | h3. Clock |
218 | 1 | Frédéric Blanc | |
219 | 76 | Frédéric Blanc | le mode auto ne détecte pas le 125MHz(FCLK_CLK0) mais semble prendre 50MHz, d'ou une erreur de x2.5 (overcloking) |
220 | 75 | Frédéric Blanc | !clipboard-202310301446-afoxm.png! |
221 | |||
222 | parametre a modifier dans le zynq pour avoir la bonne fréquence 125MHz(FCLK_CLK0) |
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223 | |||
224 | !clipboard-202310301443-qm7dq.png! |
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225 | 68 | Frédéric Blanc | |
226 | 74 | Frédéric Blanc | h3. Bascule D flip-flop |
227 | |||
228 | !clipboard-202310301320-froal.png! |
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229 | util ff |
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230 | |||
231 | 77 | Frédéric Blanc | h3. PULSE |
232 | |||
233 | !clipboard-202310301452-mrz0e.png! |
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234 | 78 | Frédéric Blanc | bascule D en mode FDCE, wizard clock 400Mhz bus par défaul 50Mhz (125MHz réel) |
235 | 77 | Frédéric Blanc | |
236 | 79 | Frédéric Blanc | h2. RAM |
237 | |||
238 | 87 | Frédéric Blanc | |
239 | voir tuto document:"tuto vivado memoire partagé CPU-FPGA" |
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240 | |||
241 | 82 | Frédéric Blanc | https://forum.redpitaya.com/viewtopic.php?t=1795 |
242 | |||
243 | 83 | Frédéric Blanc | !clipboard-202311070920-og7mi.png! |
244 | |||
245 | 81 | Frédéric Blanc | !clipboard-202311061559-umyvt.png! |
246 | |||
247 | 80 | Frédéric Blanc | https://forum.redpitaya.com/viewtopic.php?t=1675 |
248 | |||
249 | 79 | Frédéric Blanc | https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html/ |
250 | |||
251 | How to control AXI DMA and/or BRAM cores in a ZYNQ |
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252 | |||
253 | https://electronics.stackexchange.com/questions/482233/how-to-control-axi-dma-and-or-bram-cores-in-a-zynq |
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254 | |||
255 | 84 | Frédéric Blanc | tuto a verifier |
256 | https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/controlling-led-brightness-by-pwm-on-minized |
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257 | |||
258 | 85 | Frédéric Blanc | https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/path-to-programmable---lab-8---pwm-controller |
259 | |||
260 | 1 | Frédéric Blanc | h3. tuto Web |
261 | 19 | Frédéric Blanc | |
262 | 21 | Frédéric Blanc | https://github.com/lvillasen/RedPitaya-Hello-World |
263 | |||
264 | 19 | Frédéric Blanc | https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html |
265 | 7 | Frédéric Blanc | |
266 | https://antonpotocnik.com/?p=487360 |
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267 | 29 | Frédéric Blanc | |
268 | https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf |
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269 | 30 | Frédéric Blanc | |
270 | http://jmfriedt.free.fr/redpitaya.pdf |
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271 | 31 | Frédéric Blanc | |
272 | http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf |
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273 | 60 | Frédéric Blanc | |
274 | RAM |
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275 | |||
276 | https://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynq |
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277 | 61 | Frédéric Blanc | |
278 | 1 | Frédéric Blanc | https://elinux.org/Connect_a_ARM_Microcontroller_to_a_FPGA_using_its_Extended_Memory_Interface_%28EMI%29 |
279 | 64 | Frédéric Blanc | |
280 | http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorial.pdf |
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281 | 79 | Frédéric Blanc | |
282 | https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html/ |