Frédéric Blanc » Red Pitaya

Shared RAM CPU FPGA » History » Revision 11

Revision 10 (Frédéric Blanc, 2023-12-07 13:40) → Revision 11/15 (Frédéric Blanc, 2023-12-11 15:27)

h1. Shared RAM CPU FPGA 

 

 h2. commande pour ecrire dans la DDR *monitor* 

 Usage: 
     read addr: address 
     write addr: address value 
     read analog mixed signals: -ams 
     set slow DAC: -sdac AO0 AO1 AO2 AO3 [V] 

 https://redpitaya.readthedocs.io/en/latest/appsFeatures/command_line_tools/com_line_tool.html#accessing-system-registers 

 code source 
 https://github.com/RedPitaya/RedPitaya/tree/master/Test/monitor 

 h2. Cache 

 https://docs.xilinx.com/r/en-US/oslib_rm/Arm-Cortex-A53-64-bit-Processor-Cache-Functions 
 https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexa9/xil_cache.h 

 

 h2. Create Block 

 !clipboard-202311131026-thzpz.png! 

 h3. Configure BRAM 
 !clipboard-202311131035-htcja.png! 
 Memory Type: True Dual Port RAM 
 !clipboard-202311131039-uqbax.png! 
 (Disable) Enable Safety Circuit 
 !clipboard-202311131043-wbbsw.png! 
 Run Connection Automation axi_gpio_0/S_AXI 
 !clipboard-202311131043-jszfx.png! 
 after Automation 

 !clipboard-202311131045-aisy4.png! 
 Run Connection Automation axi_gpio_0/gpio 
 !clipboard-202311131047-kzdy7.png! 
 After Automation 

 !clipboard-202311131052-jlgz6.png! 
 Run Connection Automation axi_gpio_0/gpio 
 !clipboard-202311131051-p1my8.png! 
 After Automation 

 !clipboard-202311131055-lg6tx.png! 
 Address Editor 

 

 h2. Ecriture dans la RAM 

 Utilisation du programme : 
 document:"memrw.c" 

 

 h2. Source: 

 https://support.xilinx.com/s/question/0D52E00006hplPeSAI/axi4-stream-fifo-keeps-data?language=en_US 
 https://forum.digilent.com/topic/3822-what-is-the-fastest-way-to-save-pl-data/