Shared RAM CPU FPGA¶

Cache¶

https://docs.xilinx.com/r/en-US/oslib_rm/Arm-Cortex-A53-64-bit-Processor-Cache-Functions

Create Block¶

Configure BRAM

Memory Type: True Dual Port RAM

(Disable) Enable Safety Circuit

Run Connection Automation axi_gpio_0/S_AXI

after Automation¶

Run Connection Automation axi_gpio_0/gpio

After Automation

Run Connection Automation axi_gpio_0/gpio

After Automation

Address Editor

Ecriture dans la RAM¶

Utilisation du programme :
memrw.c

Source:¶

https://support.xilinx.com/s/question/0D52E00006hplPeSAI/axi4-stream-fifo-keeps-data?language=en_US
https://forum.digilent.com/topic/3822-what-is-the-fastest-way-to-save-pl-data/