Xilink Vivado » History » Revision 20
Revision 19 (Frédéric Blanc, 2023-04-25 11:19) → Revision 20/94 (Frédéric Blanc, 2023-04-25 11:28)
h1. Xilink Vivado h2. installation Windows h3. Vivado 2022.2 Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. <pre><code class="shell"> dir D:\Public\RedPitaya-FPGA vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 </code></pre> !clipboard-202304201305-exdsl.png! We recommend Vivado 2020.1 h3. Vivado 2020.1 Tcl Console <pre><code class="shell"> cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl </code></pre> !clipboard-202304251008-te1ah.png! pour éviter cette erreur copier le dossier core dans ../tmp/ attachment:cores.zip h4. Bitstream !clipboard-202304251107-19zhk.png! le fichier bitstream doit être remplacer le fichier /dev/xdevcfg h3. tuto Web https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html https://antonpotocnik.com/?p=487360