Xilink Vivado » History » Revision 25
Revision 24 (Frédéric Blanc, 2023-04-26 14:52) → Revision 25/94 (Frédéric Blanc, 2023-04-26 14:59)
h1. Xilink Vivado
h2. installation Windows
h3. Vivado 2022.2
Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory
On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell.
<pre><code class="shell">
dir D:\Public\RedPitaya-FPGA
vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94
</code></pre>
!clipboard-202304201305-exdsl.png!
We recommend Vivado 2020.1
h3. Vivado 2020.1
h2. Création d'un nouveau projet
Clone the repositiry
Create a new project with Vivado.
Select the device xc7z010clg400-1
Add the constraint redpitaya.xdc and verilog counter.v files from the repository.
Create a new Block Design according to the following instructions to creat a block diagram similar to Fig. 1.Binary_Counter.
Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options.
Add Module counter.v from the menu.
clic doit
!clipboard-202304261446-zpxnx.png!
Add a Binary Counter from thr Add IP menu.
Add a port called led_o with components from 7 down to 0.
!clipboard-202304261452-qlhno.png!
connect
!clipboard-202304261459-b9oyj.png!
From the menu click on Validate Design
In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper'
Proceed to run Synthesis, Implementation and Bitstream Generation
Find the bitstream file (you may use the command 'find . -name *bit')
Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit)
clic doit
!clipboard-202304261446-zpxnx.png!
Tcl Console
<pre><code class="shell">
cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink
source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl
</code></pre>
!clipboard-202304251008-te1ah.png!
pour éviter cette erreur copier le dossier core dans ../tmp/
attachment:cores.zip
h4. Bitstream
!clipboard-202304251107-19zhk.png!
le fichier bitstream doit être remplacer le fichier /dev/xdevcfg
h3. tuto Web
https://github.com/lvillasen/RedPitaya-Hello-World
https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html
https://antonpotocnik.com/?p=487360