Frédéric Blanc » Hyperproto_FPGA

DLPC410 » History » Revision 10

Revision 9 (Frédéric Blanc, 2017-04-27 14:36) → Revision 10/13 (Frédéric Blanc, 2017-04-27 14:39)

h1. DLPC410 

 !functional_block_diagram_dlpc410.png! 
 |_.BLOCK |_.NAME|_.BUS|_.TYPE|_.DLPC I/O|_.DESCRIPTION| 
 |/3=.*A* |*DDC_DIN_A*|16|LVDS|=.I|Data A bus Input| 
          |*DVALID_A*| |LVDS|=.I|Bank A Valid Input Signal| 
          |*DDC_DCLK_A*| |LVDS|=.I|Bank A Input Clock| 
 |/3=.*B* |*DDC_DIN_B*|16|LVDS|=.I|Data B bus Input| 
          |*DVALID_B*| |LVDS|=.I|Bank B Valid Input Signal| 
          |*DDC_DCLK_B*| |LVDS|=.I|Bank B Input Clock| 
 |/3=.*C* |*DDC_DIN_C*|16|LVDS|=.I|Data C bus Input| 
          |*DVALID_C*| |LVDS|=.I|Bank C Valid Input Signal| 
          |*DDC_DCLK_C*| |LVDS|=.I|Bank C Input Clock| 
 |/3=.*D* |*DDC_DIN_D*|16|LVDS|=.I|Data D bus Input| 
          |*DVALID_D*| |LVDS|=.I|Bank D Valid Input Signal| 
          |*DDC_DCLK_D*| |LVDS|=.I|Bank D Input Clock| 
 |/10=.*Ctrl_Sig_In* |COMP_DATA| |SE|=.I|Compliment Data (0 <--> 1)| 
          |NS_FLIP| |SE|=.I|Top/Bottom image flip on DMD| 
          |STEPVCC| |SE|=.I|Not Used| 
          |WDT_ENBLZ| |SE|=.I|DMD Mirror Clocking PulseWatchdog Timer Enable| 
          |PWR_FLOAT| |SE|=.I|DMD Power Good indicator| 
          |ROWMD|2|SE|=.I|DMD Row Mode| 
          |ROWAD|11|SE|=.I|DMD Row Address| 
          |RST2BLK| |SE|=.I|Dual Block Reset bit| 
          |BLKMD|2|SE|=.I|Block Mode| 
          |BLKAD|11|SE|=.I|Block Address| 
 |/5=.*Info Out* |RST_ACTIVE| |SE|=.O|DMD Reset in Progress| 
          |INIT_ACTIVE| |SE|=.O|DLPC410 Initilization Routine Active| 
          |ECP2_FINISHED| |SE|=.O|DLPR410 Initialization Routine Complete| 
          |DMD_TYPE|4|SE|=.O| DMD Attached Type| 
          |DDC_VERSION|3|SE|=.O| DLPC410 Firmware Rev Number| 
 |*RESET*|*ARST*||SE|I|DLPC410 Reset| 
 |*CLOCK*|CLKIN_R||SE|I|Reference Clock| 

 document:"DLPC410 DLP Digital Controller [dlps024c.pdf]"