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Frédéric Blanc, 2017-04-27 14:40

DLPC410¶

BLOCK	NAME	BUS	TYPE	DLPC I/O	DESCRIPTION
A	DDC_DIN_A	16	LVDS	I	Data A bus Input
	DVALID_A		LVDS	I	Bank A Valid Input Signal
	DDC_DCLK_A		LVDS	I	Bank A Input Clock
B	DDC_DIN_B	16	LVDS	I	Data B bus Input
	DVALID_B		LVDS	I	Bank B Valid Input Signal
	DDC_DCLK_B		LVDS	I	Bank B Input Clock
C	DDC_DIN_C	16	LVDS	I	Data C bus Input
	DVALID_C		LVDS	I	Bank C Valid Input Signal
	DDC_DCLK_C		LVDS	I	Bank C Input Clock
D	DDC_DIN_D	16	LVDS	I	Data D bus Input
	DVALID_D		LVDS	I	Bank D Valid Input Signal
	DDC_DCLK_D		LVDS	I	Bank D Input Clock
Ctrl_Sig_In	COMP_DATA		SE	I	Compliment Data (0 <--> 1)
	NS_FLIP		SE	I	Top/Bottom image flip on DMD
	STEPVCC		SE	I	Not Used
	WDT_ENBLZ		SE	I	DMD Mirror Clocking PulseWatchdog Timer Enable
	PWR_FLOAT		SE	I	DMD Power Good indicator
	ROWMD	2	SE	I	DMD Row Mode
	ROWAD	11	SE	I	DMD Row Address
	RST2BLK		SE	I	Dual Block Reset bit
	BLKMD	2	SE	I	Block Mode
	BLKAD	11	SE	I	Block Address
Info Out	RST_ACTIVE		SE	O	DMD Reset in Progress
	INIT_ACTIVE		SE	O	DLPC410 Initilization Routine Active
	ECP2_FINISHED		SE	O	DLPR410 Initialization Routine Complete
	DMD_TYPE	4	SE	O	DMD Attached Type
	DDC_VERSION	3	SE	O	DLPC410 Firmware Rev Number
RESET	ARST		SE	I	DLPC410 Reset
CLOCK	CLKIN_R		SE	I	Reference Clock

Files (5)

functional_block_diagram_dlpc410.png (119 KB) functional_block_diagram_dlpc410.png		Frédéric Blanc, 2017-04-27 08:49
dlp_single_mode.png (21.4 KB) dlp_single_mode.png		Frédéric Blanc, 2017-04-28 13:10
dlp_dual_mode.png (23.6 KB) dlp_dual_mode.png		Frédéric Blanc, 2017-04-28 13:11
dlp_quad_mode.png (32.6 KB) dlp_quad_mode.png		Frédéric Blanc, 2017-04-28 13:12
dlp_global_mode.png (37.2 KB) dlp_global_mode.png		Frédéric Blanc, 2017-04-28 13:13