Shared RAM CPU FPGA » History » Version 2
Frédéric Blanc, 2023-11-13 10:44
| 1 | 1 | Frédéric Blanc | h1. Shared RAM CPU FPGA |
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| 3 | h2. Create Block |
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| 5 | !clipboard-202311131026-thzpz.png! |
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| 7 | 2 | Frédéric Blanc | h3. Configure BRAM |
| 8 | 1 | Frédéric Blanc | !clipboard-202311131035-htcja.png! |
| 9 | Memory Type: True Dual Port RAM |
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| 10 | !clipboard-202311131039-uqbax.png! |
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| 11 | (Disable) Enable Safety Circuit |
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| 12 | 2 | Frédéric Blanc | !clipboard-202311131043-wbbsw.png! |
| 13 | Run Connection Automation S_AXI |
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| 14 | !clipboard-202311131043-jszfx.png! |
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| 15 | after Automation |