Shared RAM CPU FPGA » History » Revision 2
Revision 1 (Frédéric Blanc, 2023-11-13 10:41) → Revision 2/15 (Frédéric Blanc, 2023-11-13 10:44)
h1. Shared RAM CPU FPGA h2. Create Block !clipboard-202311131026-thzpz.png! h3. Configure BRAM !clipboard-202311131035-htcja.png! Memory Type: True Dual Port RAM !clipboard-202311131039-uqbax.png! (Disable) Enable Safety Circuit !clipboard-202311131043-wbbsw.png! Run Connection Automation S_AXI !clipboard-202311131043-jszfx.png! after Automation