Shared RAM CPU FPGA » History » Revision 3
Revision 2 (Frédéric Blanc, 2023-11-13 10:44) → Revision 3/15 (Frédéric Blanc, 2023-11-13 10:52)
h1. Shared RAM CPU FPGA h2. Create Block !clipboard-202311131026-thzpz.png! h3. Configure BRAM !clipboard-202311131035-htcja.png! Memory Type: True Dual Port RAM !clipboard-202311131039-uqbax.png! (Disable) Enable Safety Circuit !clipboard-202311131043-wbbsw.png! Run Connection Automation axi_gpio_0/S_AXI S_AXI !clipboard-202311131043-jszfx.png! after Automation !clipboard-202311131045-aisy4.png! Run Connection Automation axi_gpio_0/gpio !clipboard-202311131047-kzdy7.png! After Automation !clipboard-202311131052-jlgz6.png! Run Connection Automation axi_gpio_0/gpio !clipboard-202311131051-p1my8.png! After Automation