Shared RAM CPU FPGA » History » Revision 4
Revision 3 (Frédéric Blanc, 2023-11-13 10:52) → Revision 4/15 (Frédéric Blanc, 2023-11-13 10:55)
h1. Shared RAM CPU FPGA
h2. Create Block
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h3. Configure BRAM
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Memory Type: True Dual Port RAM
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(Disable) Enable Safety Circuit
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Run Connection Automation axi_gpio_0/S_AXI
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after Automation
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Run Connection Automation axi_gpio_0/gpio
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After Automation
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Run Connection Automation axi_gpio_0/gpio
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After Automation
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Address Editor