Shared RAM CPU FPGA¶

Create Block¶

Configure BRAM

Memory Type: True Dual Port RAM

(Disable) Enable Safety Circuit

Run Connection Automation axi_gpio_0/S_AXI

after Automation¶

Run Connection Automation axi_gpio_0/gpio

After Automation

Run Connection Automation axi_gpio_0/gpio

After Automation

Address Editor

source:
https://support.xilinx.com/s/question/0D52E00006hplPeSAI/axi4-stream-fifo-keeps-data?language=en_US