Frédéric Blanc » Hyperproto_FPGA

h1. DLPC410

!functional_block_diagram_dlpc410.png!

|_.BLOCK |_.NAME|_.BUS|_.TYPE|_.DLPC I/O|_.DESCRIPTION|

|/3=.*A* |DDC_DIN_A|16|LVDS|I|Data A bus Input|

         |DVALID_A| |LVDS|I|Bank A Valid Input Signal|

         |DDC_DCLK_A| |LVDS|I|Bank A Input Clock|

|/3=.*B* |DDC_DIN_B|16|LVDS|I|Data B bus Input|

         |DVALID_B| |LVDS|I|Bank B Valid Input Signal|

         |DDC_DCLK_B| |LVDS|I|Bank B Input Clock|

|/3=.*C* |DDC_DIN_C|16|LVDS|I|Data C bus Input|

         |DVALID_C| |LVDS|I|Bank C Valid Input Signal|

         |DDC_DCLK_C| |LVDS|I|Bank C Input Clock|

|/3=.*D* |DDC_DIN_D|16|LVDS|I|Data D bus Input|

         |DVALID_D| |LVDS|I|Bank D Valid Input Signal|

         |DDC_DCLK_D| |LVDS|I|Bank D Input Clock|

|/3=.*Ctrl_Sig_In* |COMP_DATA| |SE|I|

|NS_FLIP| |SE|I|Top/Bottom image flip on DMD|

document:"DLPC410 DLP Digital Controller [dlps024c.pdf]"