DLPC410 » History » Revision 5
Revision 4 (Frédéric Blanc, 2017-04-27 13:44) → Revision 5/13 (Frédéric Blanc, 2017-04-27 13:57)
h1. DLPC410 !functional_block_diagram_dlpc410.png! |_.BLOCK |_.NAME|_.BUS|_.TYPE|_.DLPC I/O|_.DESCRIPTION| I/O| |/3=.*A* |DDC_DIN_A|16|LVDS|I|Data A bus Input| |DDC_DIN_A|16|LVDS|I| |DVALID_A| |LVDS|I|Bank A Valid Input Signal| |LVDS|I| |DDC_DCLK_A| |LVDS|I|Bank A Input Clock| |DDC_DCLKIN_A| |LVDS|I| |/3=.*B* |DDC_DIN_B|16|LVDS|I|Data B bus Input| |DDC_DIN_A|16|LVDS|I| |DVALID_B| |LVDS|I|Bank B Valid Input Signal| |DVALID_A| |LVDS|I| |DDC_DCLK_B| |LVDS|I|Bank B Input Clock| |DDC_DCLKIN_A| |LVDS|I| |/3=.*C* |DDC_DIN_C|16|LVDS|I|Data C bus Input| |DDC_DIN_A|16|LVDS|I| |DVALID_C| |LVDS|I|Bank C Valid Input Signal| |DVALID_A| |LVDS|I| |DDC_DCLK_C| |LVDS|I|Bank C Input Clock| |DDC_DCLKIN_A| |LVDS|I| |/3=.*D* |DDC_DIN_D|16|LVDS|I|Data D bus Input| |DDC_DIN_A|16|LVDS|I| |DVALID_D| |LVDS|I|Bank D Valid Input Signal| |DVALID_A| |LVDS|I| |DDC_DCLK_D| |LVDS|I|Bank D Input Clock| |/3=.*Ctrl_Sig_In* |COMP_DATA| |SE|I| |NS_FLIP| |SE|I|Top/Bottom image flip on DMD| |DDC_DCLKIN_A| |LVDS|I| document:"DLPC410 DLP Digital Controller [dlps024c.pdf]"