Frédéric Blanc » Hyperproto_FPGA

p=. *Wiki DLP4100*

h1. Overview 

!hyperholo.png! 

The DLP® Discovery™ 4100 (D4100) is the latest in a series of spatial light modulation development kits from Texas 

Instruments.  Users of the D4100 Starter Kit have the ability to manipulate visible, ultraviolet and near-infrared light 

with extremely high performance and high resolution. 

 The D4100 offers developers a flexible platform to design products to fit most any application using the proven 

reliability of DLP technology. 

!d4100_block_diagram.png!

Fig 1: System Overview 

|_.New version |_.Actual|_.Name|

|DLPC410|DDC4100 (FPGA X5VLX30)|Digital Controller for Discovery 4100 chipset|

|DLPR410|XCF16|PROM for Discovery 4100 chipset|

|DLPA200|DAD2000|DMD Micromirror Driver|

document:"DLPC410 DLP Digital Controller [dlps024c.pdf]"

h1. Configuration Jumpers, Switch and LED 

!d4100_configuration.png!

Fig 2: D4100 Controller Configuration Jumpers, Switch and LED

*LED1 - USB status*

CY7C68013A_128

*LED2 - APPSFPGA status*

(FPGA PIN N14) 

|_.LED|_.Status|

|RED|BAD|

|GREEN|OK|

*LED3 - DDC4000 status*

|_.LED|_.Status|

|RED|BAD|

|GREEN|OK|

*LED9..12 - LED status*

LED9 - DDC_LED0 Status LED for the DDC4000

The LED0 signal is typically connected to an LED to show that the DLPC410 is operating normally.

The signal is 1 Hz with 50% duty cycle, otherwise known as the heartbeat LED10 - DDC_LED1 Status

LED for the DDC4000. The LED1 signal is typically connected to an LED indicator to show the status

of system initialization and the status of the clock circuits. The LED1 signalis asserted only 

when system initialization is complete and clock circuits are initialized. Logically, these 

signals are ANDed together to show an indication of the health of the system. If the Phase Locked 

Loop (PLL) connected to the data clock and the DMDclock are functioning correctly after system

initialization, the LED will be illuminated

LED11 - VLED0 This logic is to be defined by the APPSFPGA application. Drive low to turn on the led. Drive high to

turn off the led(FPGA PIN AK19).

LED12 - VLED1 This logic is to be defined by the APPSFPGA application. Drive low to turn on the led. Drive high to

turn off the led(FPGA PIN AJ19).

*J2 – EXP Voltage Select*

*J4 – Used to select the revision of firmware loaded from the PROM to the APPSFPGA.*

|_.Jumper Position|_.Revision Version|

|open|0|

|close|1|

*J5 – Shared USB signal disabled*

|_.Jumper Position|_.USB Signals|

|0-1|Disconnected from FPGA |

|1-2|Connected to FPGA|

|2-3|Automatically connect USB signals 

     to FPGA when USB is connected to 

     host PC |

*J7 – USB EEPROM Programming Header* 

Used to temporally disconnect the USB EEPROM fromthe device so the device can load its internal 

boot loader rather than any code in the EEPROM. Install J8 for Cypress internal boot loader. 

*J10 – DAD2000 B Output Enable*

Used to enable the outputs for DAD2000 B. This needs to be enabled only if using the 1080p DMD, 

otherwise this can be disabled. 

|_.Jumper Position|_.DAD2000 B Outputs|

|open|Disabled|

|close|Enabled|

*J11 – Used to select the revision of firmware loaded from the PROM to the DDC4100 (FPGA X5VLX30).*

|_.Jumper Position|_.Revision Version|

|open|0|

|close|1|

*SW1 - Dipswitches*

Functionality defined by APPSFPGA programming. In default test pattern code:

|_.Switch Number|_.Effect|_.FPGA PIN|

|1 |ON = float – float all mirrors|G20|

|2 |ON = counter halt – stop counter, this will freeze the image on the DMD|G21|

|3 |ON = complement data – causes DDC 4000 to complement all data it receives|F20|

|4 |ON = north/south flip – causes the DDC 4000

to reverse order of row loading, effectively

flipping the image|G22|

|5 |Dictates the type of reset being used LSB ON = 1|H15|

|6 |Dictates the type of reset being used MSB ON = 1|H14|

||00 : single block phased reset|

||01 : dual block phased reset|

||10 : global reset|

||11 : quad block phased reset|

|7 |ON = Row Address Mode|H12|

|8 |ON = WDT Enable, disables other resets|J14|

*SW2 - Push Button Momentary Switch*

Functionality defined by APPSFPGA. This switch is used for *APPS_LOGIC_RESET* in the default code.

(FPGA PIN T24)

*SW3 - Push Button Momentary Switch*

Functionality defined by APPSFPGA. This switch is used for *APPS_LOGIC_MIRROR_FLOAT* in the default code.

(FPGA PIN P10)

*SW4 - POWER STANDBY*

h1. Power Down

*%{background:yellow}To ensure long term reliability of the DMD, a shutdown procedure must be executed.%*

Prior to power removal, assert the PWR_FLOAT (Table 1) signal and allow approximately 300μs for the procedure to

complete. This procedure will assure the mirrors are in a flat state. For more details, please refer to the

appropriate DMD document.

h1. APPSFPGA 

The APPSFPGA contains the Applications FPGA Sample Code for the DDC4100. This sample code

cycles through test patterns and is meant to offer an example of code that meets the DDC4100

specification. It has been written to implement all features of the DDC4100, such as the complement

function and all mirror reset types, as explained in later sections. This sample code also addresses

additional operational requirements for the DDC4100 interface which should be observed.

|_.Signal Name |_.Description|

|CLK_I |Input clock (50 MHz)|

|ARSTZ |Active low, asynchronous system reset (connected to flip switch)|

|IN_PWR_FLOAT_I |Float all mirrors in preparation for system shutdown (connect to push-button switch)|

|FINISHED_IV_O |Indicates when applications FPGA has finished initialization (connected to LED)|

|IN_RST_ACTIVE_I |Asserted while a mirror reset is being executed|

|IN_INIT_ACTIVE_I |Asserted while DDC4100 is initializing|

|IN_DIP_SW_I |Dip switch inputs|

|FINISHED_IV_O |Indicates when applications FPGA has finished initialization (connected to LED)|

|CLK_R |Reference clock to DDC4100 (50MHz)|

|DOUT_A[15:0] |Output data A to DDC4100 (400MHz DDR)|

|DOUT_B[15:0] |Output data B to DDC4100 (400MHz DDR)|

|DOUT_C[15:0] |Output data C to DDC4100 (400MHz DDR)|

|DOUT_D[15:0] |Output data D to DDC4100 (400MHz DDR)|

|DCLK_A |Output data clock to DDC4100 (400MHz)|

|DVALID_A |Output data valid to DDC4100 used to qualify data|

|ROWMD[1:0] |Output row mode to DDC4100|

|ROWAD[10:0] |Output row address to DDC4100|

|STEPVCC |Output to indicate status of vcc step|

|COMP_DATA |Output to cause DDC4100 to complement all data|

|NS_FLIP |Output to cause DDC4100 to reverse order of row loading|

|BLKAD |Output block address to DDC4100|

|BLKMD |Output block mode to DDC4100|

|WDT_ENABLEZ |Output watch dog timer|

*Getting Started*

The following steps should be followed in starting board operation using the default APPSFPGA code installed at the

factory :

1.) Connect 5V, 5 A power supply to the supplied power cable. Connect the power cable to J12 with the power

supply OFF.

2.) Confirm all SW2 switches are in the OFF position. Confirm all 5 H1 jumpers are in place. If using a 1080p

DMD confirm J11 is installed.

3.) Connect the DMD to the board with the flex cable(s). One flex cable attached to J13 is used for XGA DMDs,

two flex cables attached to J14 and J14 are used for 1080p DMD.

4.) Turn the power supply ON. D2 and D3 should briefly display red then green to indicate APPSFPGA and

DDC4000 configuration. *D9 should flash green at 1 Hz*. D10 should display green. The DMD will repeatedly

cycle through several test patterns.

*%{background:yellow}To stop operation :

1.) Press SW3 to float the DMD, then turn power OFF.%*

document:"DDC4100 Applications FPGA Sample Code Guide [2510445.pdf]"

h1. EXP Expansion Connectors

To connect to an Avnet EXP compatible motherboard product.

Board design includes additional LVDS pairs to support 64 bit LVDS connection through EXP

connectors with a custom interface board.

64 IO LVDS

28 IO SE

2 CLK_IN LVDS (FPGA PIN H19,H20 ; H18,J17) and SE (FPGA PIN J20 ; J16)

2 CLK_OUT LVDS (FPGA PIN U31,U32 ; AC3,AB2) and SE (FPGA PIN J21 ; J15)

h1. RAM

A 64 bit DDR2 SODIMM connector provides high speed memory connection to the APPSFPGA. Memory

controller design for the APPSFPGA is not included. For a memory controller reference design

document:"Xilinx Memory Interface Generator (MIG) User Guide [ug086.pdf]"

h1. USB

The USB EEPROM does not have any code only VID/PID data.  Here is a sequence of USB initialization:    

    When a board is plugged in by USB the Windows D4100 USB driver sees the unprogrammed TI VID/PID.  (The Windows D4100 USB driver is installed with the Explorer software.)

    Then it loads a program directly into the Cypress USB (not the EEPROM) and runs it.  (This loads the firmware through USB)

    This sets the Cypress VID/PID to show that the part is programmed and allows communication with the Board.

This is only the first part.  To communicate with the DMD a different APPS_FPGA program (D4100_GUI_FPGA.bin) must be loaded that can communicate with the Cypress USB.

When the D4100 Explorer is started it checks to see if D4100_GUI_FPGA.bin is loaded in the FPGA and programs the FPGA if it not.

This program can also be loaded by invoking the DLL function directly from another program (see the API Programmer’s Guide)

Once loaded then the other API DLL functions can be used to load and reset image data. 

*%{background:yellow}If you have one of the ViALUX ALP versions you will need to contact them concerning this since their software uses proprietary communication protocols with the D4100.%*