Shared RAM CPU FPGA » History » Version 5
Frédéric Blanc, 2023-11-13 13:49
| 1 | 1 | Frédéric Blanc | h1. Shared RAM CPU FPGA |
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| 3 | h2. Create Block |
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| 4 | |||
| 5 | !clipboard-202311131026-thzpz.png! |
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| 6 | |||
| 7 | 2 | Frédéric Blanc | h3. Configure BRAM |
| 8 | 1 | Frédéric Blanc | !clipboard-202311131035-htcja.png! |
| 9 | Memory Type: True Dual Port RAM |
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| 10 | !clipboard-202311131039-uqbax.png! |
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| 11 | (Disable) Enable Safety Circuit |
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| 12 | 2 | Frédéric Blanc | !clipboard-202311131043-wbbsw.png! |
| 13 | 3 | Frédéric Blanc | Run Connection Automation axi_gpio_0/S_AXI |
| 14 | 2 | Frédéric Blanc | !clipboard-202311131043-jszfx.png! |
| 15 | 1 | Frédéric Blanc | after Automation |
| 16 | 3 | Frédéric Blanc | |
| 17 | !clipboard-202311131045-aisy4.png! |
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| 18 | Run Connection Automation axi_gpio_0/gpio |
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| 19 | !clipboard-202311131047-kzdy7.png! |
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| 20 | After Automation |
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| 21 | |||
| 22 | !clipboard-202311131052-jlgz6.png! |
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| 23 | Run Connection Automation axi_gpio_0/gpio |
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| 24 | !clipboard-202311131051-p1my8.png! |
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| 25 | After Automation |
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| 26 | 4 | Frédéric Blanc | |
| 27 | !clipboard-202311131055-lg6tx.png! |
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| 28 | Address Editor |
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| 29 | 5 | Frédéric Blanc | |
| 30 | source: |
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| 31 | https://support.xilinx.com/s/question/0D52E00006hplPeSAI/axi4-stream-fifo-keeps-data?language=en_US |