Xilink Vivado » History » Version 36
Frédéric Blanc, 2023-05-16 15:14
1 | 1 | Frédéric Blanc | h1. Xilink Vivado |
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3 | h2. installation Ubuntu 20.04 |
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4 | 33 | Frédéric Blanc | |
5 | sur le site de xilinx telecharger: |
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6 | https://www.xilinx.com/support/download.html |
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7 | 35 | Frédéric Blanc | Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer |
8 | 33 | Frédéric Blanc | |
9 | 34 | Frédéric Blanc | *en root* |
10 | 33 | Frédéric Blanc | |
11 | <pre><code class="shell"> |
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12 | chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
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13 | 36 | Frédéric Blanc | sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
14 | 33 | Frédéric Blanc | </code></pre> |
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16 | 32 | Frédéric Blanc | |
17 | https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/ |
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18 | |||
19 | 1 | Frédéric Blanc | h2. installation Windows |
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21 | 6 | Frédéric Blanc | |
22 | 5 | Frédéric Blanc | h3. Vivado 2022.2 |
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24 | 2 | Frédéric Blanc | Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory |
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26 | On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. |
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27 | 3 | Frédéric Blanc | |
28 | <pre><code class="shell"> |
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29 | dir D:\Public\RedPitaya-FPGA |
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30 | vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 |
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31 | </code></pre> |
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32 | 4 | Frédéric Blanc | |
33 | !clipboard-202304201305-exdsl.png! |
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34 | 5 | Frédéric Blanc | |
35 | We recommend Vivado 2020.1 |
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36 | 7 | Frédéric Blanc | |
37 | 8 | Frédéric Blanc | h3. Vivado 2020.1 |
38 | 7 | Frédéric Blanc | |
39 | 22 | Frédéric Blanc | h2. Création d'un nouveau projet |
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41 | 27 | Frédéric Blanc | soource: https://github.com/lvillasen/RedPitaya-Hello-World |
42 | 24 | Frédéric Blanc | |
43 | Clone the repositiry |
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44 | |||
45 | Create a new project with Vivado. |
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46 | |||
47 | Select the device xc7z010clg400-1 |
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48 | |||
49 | Add the constraint redpitaya.xdc and verilog counter.v files from the repository. |
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50 | |||
51 | Create a new Block Design according to the following instructions to creat a block diagram similar to Fig. 1.Binary_Counter. |
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52 | |||
53 | Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options. |
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54 | |||
55 | Add Module counter.v from the menu. |
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56 | |||
57 | clic doit |
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58 | !clipboard-202304261446-zpxnx.png! |
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59 | |||
60 | Add a Binary Counter from thr Add IP menu. |
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61 | |||
62 | Add a port called led_o with components from 7 down to 0. |
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63 | |||
64 | !clipboard-202304261452-qlhno.png! |
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65 | |||
66 | 25 | Frédéric Blanc | connect |
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68 | 28 | Frédéric Blanc | !clipboard-202304261515-hhbvn.png! |
69 | 25 | Frédéric Blanc | |
70 | 24 | Frédéric Blanc | From the menu click on Validate Design |
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72 | In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper' |
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73 | |||
74 | 26 | Frédéric Blanc | !clipboard-202304261503-3iuu2.png! |
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76 | 24 | Frédéric Blanc | Proceed to run Synthesis, Implementation and Bitstream Generation |
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78 | Find the bitstream file (you may use the command 'find . -name *bit') |
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79 | |||
80 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
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81 | |||
82 | 22 | Frédéric Blanc | clic doit |
83 | 23 | Frédéric Blanc | !clipboard-202304261446-zpxnx.png! |
84 | 22 | Frédéric Blanc | |
85 | 10 | Frédéric Blanc | Tcl Console |
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87 | 9 | Frédéric Blanc | <pre><code class="shell"> |
88 | cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink |
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89 | source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl |
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90 | </code></pre> |
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91 | |||
92 | 11 | Frédéric Blanc | !clipboard-202304251008-te1ah.png! |
93 | 17 | Frédéric Blanc | pour éviter cette erreur copier le dossier core dans ../tmp/ |
94 | 11 | Frédéric Blanc | |
95 | 16 | Frédéric Blanc | attachment:cores.zip |
96 | 12 | Frédéric Blanc | |
97 | 18 | Frédéric Blanc | h4. Bitstream |
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99 | !clipboard-202304251107-19zhk.png! |
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101 | 20 | Frédéric Blanc | |
102 | le fichier bitstream doit être remplacer le fichier /dev/xdevcfg |
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103 | |||
104 | 1 | Frédéric Blanc | h3. tuto Web |
105 | 19 | Frédéric Blanc | |
106 | 21 | Frédéric Blanc | https://github.com/lvillasen/RedPitaya-Hello-World |
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108 | 19 | Frédéric Blanc | https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html |
109 | 7 | Frédéric Blanc | |
110 | https://antonpotocnik.com/?p=487360 |
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111 | 29 | Frédéric Blanc | |
112 | https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf |
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113 | 30 | Frédéric Blanc | |
114 | http://jmfriedt.free.fr/redpitaya.pdf |
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115 | 31 | Frédéric Blanc | |
116 | http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf |