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Wiki DLP4100 » History » Version 52

Frédéric Blanc, 2017-05-02 09:51

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p=. *Wiki DLP4100*
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h1. Overview 
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!hyperholo.png! 
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The DLP® Discovery™ 4100 (D4100) is the latest in a series of spatial light modulation development kits from Texas 
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Instruments.  Users of the D4100 Starter Kit have the ability to manipulate visible, ultraviolet and near-infrared light 
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with extremely high performance and high resolution. 
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 The D4100 offers developers a flexible platform to design products to fit most any application using the proven 
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reliability of DLP technology. 
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!d4100_block_diagram.png!
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Fig 1: System Overview 
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|_.New version |_.Actual|_.Name|
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|DLPC410|DDC4100 (FPGA X5VLX30)|Digital Controller for Discovery 4100 chipset|
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|DLPR410|XCF16P|PROM for Discovery 4100 chipset|
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|DLPA200|DAD2000|DMD Micromirror Driver|
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document:"DLPC410 DLP Digital Controller [dlps024c.pdf]"
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h1. Configuration Jumpers, Switch and LED 
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!d4100_configuration.png!
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Fig 2: D4100 Controller Configuration Jumpers, Switch and LED
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h2. LED1 - USB status
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CY7C68013A_128
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h2. LED2 - APPSFPGA status
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(FPGA PIN N14) 
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|_.LED|_.Status|
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|RED|BAD|
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|GREEN|OK|
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h2. LED3 - DDC4000 status
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|_.LED|_.Status|
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|RED|BAD|
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|GREEN|OK|
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h2. LED9..12 - LED status
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*LED9* - DDC_LED0 Status LED for the DDC4000
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The LED9 signal is typically connected to an LED to show that the DLPC410 is operating normally.
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The signal is 1 Hz with 50% duty cycle, otherwise known as the heartbeat 
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*LED10* - DDC_LED1 Status
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LED for the DDC4000. The LED1 signal is typically connected to an LED indicator to show the status
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of system initialization and the status of the clock circuits. The LED1 signalis asserted only 
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when system initialization is complete and clock circuits are initialized. Logically, these 
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signals are ANDed together to show an indication of the health of the system. If the Phase Locked 
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Loop (PLL) connected to the data clock and the DMDclock are functioning correctly after system
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initialization, the LED will be illuminated
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*LED11* - VLED0 This logic is to be defined by the APPSFPGA application. Drive low to turn on the led. Drive high to
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turn off the led(FPGA PIN AK19).
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*LED12* - VLED1 This logic is to be defined by the APPSFPGA application. Drive low to turn on the led. Drive high to
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turn off the led(FPGA PIN AJ19).
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h2. JUMPERS
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*J2 – EXP Voltage Select*
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*J4 – Used to select the revision of firmware loaded from the PROM to the APPSFPGA.*
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|_.Jumper Position|_.Revision Version|
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|open|0|
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|close|1|
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*J5 – Shared USB signal disabled*
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|_.Jumper Position|_.USB Signals|
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|0-1|Disconnected from FPGA |
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|1-2|Connected to FPGA|
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|2-3|Automatically connect USB signals 
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     to FPGA when USB is connected to 
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     host PC |
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*J7 – USB EEPROM Programming Header* 
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Used to temporally disconnect the USB EEPROM fromthe device so the device can load its internal 
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boot loader rather than any code in the EEPROM. Install J8 for Cypress internal boot loader. 
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*J10 – DAD2000 B Output Enable*
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Used to enable the outputs for DAD2000 B. This needs to be enabled only if using the 1080p DMD, 
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otherwise this can be disabled. 
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|_.Jumper Position|_.DAD2000 B Outputs|
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|open|Disabled|
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|close|Enabled|
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*J11 – Used to select the revision of firmware loaded from the PROM to the DDC4100 (FPGA X5VLX30).*
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|_.Jumper Position|_.Revision Version|
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|open|0|
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|close|1|
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h2. SWITCH
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*SW1 - Dipswitches*
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Functionality defined by APPSFPGA programming. In default test pattern code:
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|_.Switch Number|_.Effect|_.FPGA PIN|
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|1 |ON = float – float all mirrors|G20|
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|2 |ON = counter halt – stop counter, this will freeze the image on the DMD|G21|
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|3 |ON = complement data – causes DDC 4000 to complement all data it receives|F20|
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|4 |ON = north/south flip – causes the DDC 4000
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to reverse order of row loading, effectively
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flipping the image|G22|
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|5 |Dictates the type of reset being used LSB ON = 1|H15|
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|6 |Dictates the type of reset being used MSB ON = 1|H14|
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||00 : single block phased reset|
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||01 : dual block phased reset|
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||10 : global reset|
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||11 : quad block phased reset|
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|7 |ON = Row Address Mode|H12|
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|8 |ON = WDT Enable, disables other resets|J14|
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*SW2 - Push Button Momentary Switch*
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Functionality defined by APPSFPGA. This switch is used for *APPS_LOGIC_RESET* in the default code.
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(FPGA PIN T24)
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*SW3 - Push Button Momentary Switch*
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Functionality defined by APPSFPGA. This switch is used for *APPS_LOGIC_MIRROR_FLOAT* in the default code.
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(FPGA PIN P10)
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*SW4 - POWER STANDBY*
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h1. Power Down
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*%{background:yellow}To ensure long term reliability of the DMD, a shutdown procedure must be executed.%*
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Prior to power removal, assert the PWR_FLOAT (Table 1) signal and allow approximately 300μs for the procedure to
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complete. This procedure will assure the mirrors are in a flat state. For more details, please refer to the
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appropriate DMD document.
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h1. APPSFPGA 
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The APPSFPGA contains the Applications FPGA Sample Code for the DDC4100. This sample code
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cycles through test patterns and is meant to offer an example of code that meets the DDC4100
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specification. It has been written to implement all features of the DDC4100, such as the complement
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function and all mirror reset types, as explained in later sections. This sample code also addresses
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additional operational requirements for the DDC4100 interface which should be observed.
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|_.Signal Name |_.Description|
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|CLK_I |Input clock (50 MHz)|
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|ARSTZ |Active low, asynchronous system reset (connected to flip switch)|
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|IN_PWR_FLOAT_I |Float all mirrors in preparation for system shutdown (connect to push-button switch)|
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|FINISHED_IV_O |Indicates when applications FPGA has finished initialization (connected to LED)|
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|IN_RST_ACTIVE_I |Asserted while a mirror reset is being executed|
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|IN_INIT_ACTIVE_I |Asserted while DDC4100 is initializing|
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|IN_DIP_SW_I |Dip switch inputs|
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|FINISHED_IV_O |Indicates when applications FPGA has finished initialization (connected to LED)|
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|CLK_R |Reference clock to DDC4100 (50MHz)|
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|DOUT_A[15:0] |Output data A to DDC4100 (400MHz DDR)|
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|DOUT_B[15:0] |Output data B to DDC4100 (400MHz DDR)|
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|DOUT_C[15:0] |Output data C to DDC4100 (400MHz DDR)|
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|DOUT_D[15:0] |Output data D to DDC4100 (400MHz DDR)|
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|DCLK_A |Output data clock to DDC4100 (400MHz)|
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|DVALID_A |Output data valid to DDC4100 used to qualify data|
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|ROWMD[1:0] |Output row mode to DDC4100|
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|ROWAD[10:0] |Output row address to DDC4100|
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|STEPVCC |Output to indicate status of vcc step|
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|COMP_DATA |Output to cause DDC4100 to complement all data|
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|NS_FLIP |Output to cause DDC4100 to reverse order of row loading|
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|BLKAD |Output block address to DDC4100|
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|BLKMD |Output block mode to DDC4100|
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|WDT_ENABLEZ |Output watch dog timer|
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*Getting Started*
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The following steps should be followed in starting board operation using the default APPSFPGA code installed at the
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factory :
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1.) Connect 5V, 5 A power supply to the supplied power cable. Connect the power cable to J12 with the power
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supply OFF.
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2.) Confirm all SW2 switches are in the OFF position. Confirm all 5 H1 jumpers are in place. If using a 1080p
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DMD confirm J11 is installed.
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3.) Connect the DMD to the board with the flex cable(s). One flex cable attached to J13 is used for XGA DMDs,
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two flex cables attached to J14 and J14 are used for 1080p DMD.
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4.) Turn the power supply ON. D2 and D3 should briefly display red then green to indicate APPSFPGA and
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DDC4000 configuration. *D9 should flash green at 1 Hz*. D10 should display green. The DMD will repeatedly
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cycle through several test patterns.
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*%{background:yellow}To stop operation :
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1.) Press SW3 to float the DMD, then turn power OFF.%*
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document:"DDC4100 Applications FPGA Sample Code Guide [2510445.pdf]"
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h2. DDC4100 GUI/MEM Applications FPGASample
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!appsfpga_gui.png!
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fig. System Overview of Example Design
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!gui_appsfpga_block_diagram.png!
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fig. GUI/MEM APPS FPGA Block Diagram
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|_.Switch Number |_.Effect|
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|1 |Inject error into the Memory BIST|
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|2 |Unused|
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|3 |Unused|
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|4 |Unused|
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|5 |Unused|
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|6 |Unused|
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|7 |Unused|
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|8 |Unused|
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*MEM APPS Design*
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The DDR2 MEM APPS FPGA design contains sample code for testing a 2GB DDR2 SO-DIMM module at
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150 MHz with a burst length of four. The DDR2 module has a 64-bit data interface. The target device
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used in this design is the MT16HTF25664HY-667. The design consists of two blocks: Memory_BIST and
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Memory Controller.
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document:"Applications FPGA design that drives the DDC4100 system via USB/GUI [2510445_GUI.pdf]"
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h1. EXP Expansion Connectors
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To connect to an Avnet EXP compatible motherboard product.
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Board design includes additional LVDS pairs to support 64 bit LVDS connection through EXP
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connectors with a custom interface board.
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64 IO LVDS
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28 IO SE
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2 CLK_IN LVDS (FPGA PIN H19,H20 ; H18,J17) and SE (FPGA PIN J20 ; J16)
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2 CLK_OUT LVDS (FPGA PIN U31,U32 ; AC3,AB2) and SE (FPGA PIN J21 ; J15)
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h1. RAM
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A 64 bit DDR2 SODIMM connector provides high speed memory connection to the APPSFPGA. Memory
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controller design for the APPSFPGA is not included. For a memory controller reference design
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document:"Xilinx Memory Interface Generator (MIG) User Guide [ug086.pdf]"
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h1. USB
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The USB EEPROM does not have any code only VID/PID data.  Here is a sequence of USB initialization:    
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    When a board is plugged in by USB the Windows D4100 USB driver sees the unprogrammed TI VID/PID.  (The Windows D4100 USB driver is installed with the Explorer software.)
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    Then it loads a program directly into the Cypress USB (not the EEPROM) and runs it.  (This loads the firmware through USB)
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    This sets the Cypress VID/PID to show that the part is programmed and allows communication with the Board.
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This is only the first part.  To communicate with the DMD a different APPS_FPGA program (D4100_GUI_FPGA.bin) must be loaded that can communicate with the Cypress USB.
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When the D4100 Explorer is started it checks to see if D4100_GUI_FPGA.bin is loaded in the FPGA and programs the FPGA if it not.
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This program can also be loaded by invoking the DLL function directly from another program (see the API Programmer’s Guide)
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Once loaded then the other API DLL functions can be used to load and reset image data. 
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*%{background:yellow}If you have one of the ViALUX ALP versions you will need to contact them concerning this since their software uses proprietary communication protocols with the D4100.%*