Xilink Vivado » History » Version 41
Frédéric Blanc, 2023-05-24 09:24
1 | 1 | Frédéric Blanc | h1. Xilink Vivado |
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3 | h2. installation Ubuntu 20.04 |
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4 | 33 | Frédéric Blanc | |
5 | sur le site de xilinx telecharger: |
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6 | https://www.xilinx.com/support/download.html |
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7 | 35 | Frédéric Blanc | Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer |
8 | 33 | Frédéric Blanc | |
9 | 37 | Frédéric Blanc | |
10 | 34 | Frédéric Blanc | *en root* |
11 | 33 | Frédéric Blanc | |
12 | 1 | Frédéric Blanc | <pre><code class="shell"> |
13 | 40 | Frédéric Blanc | export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr |
14 | 39 | Frédéric Blanc | chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
15 | 36 | Frédéric Blanc | sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
16 | 33 | Frédéric Blanc | </code></pre> |
17 | 41 | Frédéric Blanc | echo $XILINXD_LICENSE_FILE |
18 | 2100@flexalter.laas.fr |
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19 | 33 | Frédéric Blanc | |
20 | 32 | Frédéric Blanc | |
21 | https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/ |
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22 | |||
23 | 1 | Frédéric Blanc | h2. installation Windows |
24 | |||
25 | 6 | Frédéric Blanc | |
26 | 5 | Frédéric Blanc | h3. Vivado 2022.2 |
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28 | 2 | Frédéric Blanc | Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory |
29 | |||
30 | On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. |
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31 | 3 | Frédéric Blanc | |
32 | <pre><code class="shell"> |
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33 | dir D:\Public\RedPitaya-FPGA |
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34 | vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 |
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35 | </code></pre> |
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36 | 4 | Frédéric Blanc | |
37 | !clipboard-202304201305-exdsl.png! |
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38 | 5 | Frédéric Blanc | |
39 | We recommend Vivado 2020.1 |
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40 | 7 | Frédéric Blanc | |
41 | 8 | Frédéric Blanc | h3. Vivado 2020.1 |
42 | 7 | Frédéric Blanc | |
43 | 22 | Frédéric Blanc | h2. Création d'un nouveau projet |
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45 | 27 | Frédéric Blanc | soource: https://github.com/lvillasen/RedPitaya-Hello-World |
46 | 24 | Frédéric Blanc | |
47 | Clone the repositiry |
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48 | |||
49 | Create a new project with Vivado. |
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50 | |||
51 | Select the device xc7z010clg400-1 |
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52 | |||
53 | Add the constraint redpitaya.xdc and verilog counter.v files from the repository. |
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54 | |||
55 | Create a new Block Design according to the following instructions to creat a block diagram similar to Fig. 1.Binary_Counter. |
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56 | |||
57 | Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options. |
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58 | |||
59 | Add Module counter.v from the menu. |
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60 | |||
61 | clic doit |
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62 | !clipboard-202304261446-zpxnx.png! |
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63 | |||
64 | Add a Binary Counter from thr Add IP menu. |
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65 | |||
66 | Add a port called led_o with components from 7 down to 0. |
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67 | |||
68 | !clipboard-202304261452-qlhno.png! |
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69 | |||
70 | 25 | Frédéric Blanc | connect |
71 | |||
72 | 28 | Frédéric Blanc | !clipboard-202304261515-hhbvn.png! |
73 | 25 | Frédéric Blanc | |
74 | 24 | Frédéric Blanc | From the menu click on Validate Design |
75 | |||
76 | In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper' |
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77 | |||
78 | 26 | Frédéric Blanc | !clipboard-202304261503-3iuu2.png! |
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80 | 24 | Frédéric Blanc | Proceed to run Synthesis, Implementation and Bitstream Generation |
81 | |||
82 | Find the bitstream file (you may use the command 'find . -name *bit') |
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83 | |||
84 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
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85 | |||
86 | 22 | Frédéric Blanc | clic doit |
87 | 23 | Frédéric Blanc | !clipboard-202304261446-zpxnx.png! |
88 | 22 | Frédéric Blanc | |
89 | 10 | Frédéric Blanc | Tcl Console |
90 | |||
91 | 9 | Frédéric Blanc | <pre><code class="shell"> |
92 | cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink |
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93 | source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl |
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94 | </code></pre> |
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95 | |||
96 | 11 | Frédéric Blanc | !clipboard-202304251008-te1ah.png! |
97 | 17 | Frédéric Blanc | pour éviter cette erreur copier le dossier core dans ../tmp/ |
98 | 11 | Frédéric Blanc | |
99 | 16 | Frédéric Blanc | attachment:cores.zip |
100 | 12 | Frédéric Blanc | |
101 | 18 | Frédéric Blanc | h4. Bitstream |
102 | |||
103 | !clipboard-202304251107-19zhk.png! |
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104 | |||
105 | 20 | Frédéric Blanc | |
106 | le fichier bitstream doit être remplacer le fichier /dev/xdevcfg |
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107 | |||
108 | 1 | Frédéric Blanc | h3. tuto Web |
109 | 19 | Frédéric Blanc | |
110 | 21 | Frédéric Blanc | https://github.com/lvillasen/RedPitaya-Hello-World |
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112 | 19 | Frédéric Blanc | https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html |
113 | 7 | Frédéric Blanc | |
114 | https://antonpotocnik.com/?p=487360 |
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115 | 29 | Frédéric Blanc | |
116 | https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf |
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117 | 30 | Frédéric Blanc | |
118 | http://jmfriedt.free.fr/redpitaya.pdf |
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119 | 31 | Frédéric Blanc | |
120 | http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf |