Project

General

Profile

Xilink Vivado » History » Version 46

Frédéric Blanc, 2023-06-02 13:54

1 1 Frédéric Blanc
h1. Xilink Vivado
2
3
h2. installation Ubuntu 20.04
4 33 Frédéric Blanc
5
sur le site de xilinx telecharger:
6
https://www.xilinx.com/support/download.html
7 35 Frédéric Blanc
Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer
8 33 Frédéric Blanc
9 37 Frédéric Blanc
10 34 Frédéric Blanc
*en root*
11 33 Frédéric Blanc
12 1 Frédéric Blanc
<pre><code class="shell">
13 42 Frédéric Blanc
sudo bash
14 40 Frédéric Blanc
export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr
15 39 Frédéric Blanc
chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin
16 36 Frédéric Blanc
sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin
17 33 Frédéric Blanc
</code></pre>
18 41 Frédéric Blanc
echo $XILINXD_LICENSE_FILE
19
2100@flexalter.laas.fr
20 33 Frédéric Blanc
21 32 Frédéric Blanc
22
https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/
23
24 1 Frédéric Blanc
h2. installation Windows
25
26 6 Frédéric Blanc
27 5 Frédéric Blanc
h3. Vivado 2022.2
28
29 2 Frédéric Blanc
Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory
30
31
On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell.
32 3 Frédéric Blanc
33
<pre><code class="shell">
34
dir D:\Public\RedPitaya-FPGA
35
vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94
36
</code></pre>
37 4 Frédéric Blanc
38
!clipboard-202304201305-exdsl.png!
39 5 Frédéric Blanc
40
We recommend Vivado 2020.1
41 7 Frédéric Blanc
42 8 Frédéric Blanc
h3. Vivado 2020.1
43 7 Frédéric Blanc
44 22 Frédéric Blanc
h2. Création d'un nouveau projet
45
46 27 Frédéric Blanc
soource: https://github.com/lvillasen/RedPitaya-Hello-World
47 24 Frédéric Blanc
48
Clone the repositiry
49
50
Create a new project with Vivado.
51
52
Select the device xc7z010clg400-1
53
54
Add the constraint redpitaya.xdc and verilog counter.v files from the repository.
55
56
Create a new Block Design according to the following instructions to creat a block diagram similar to Fig. 1.Binary_Counter.
57
58
Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options.
59
60
Add Module counter.v from the menu.
61
62
clic doit 
63
!clipboard-202304261446-zpxnx.png!
64
65
Add a Binary Counter from thr Add IP menu.
66
67
Add a port called led_o with components from 7 down to 0.
68
69
!clipboard-202304261452-qlhno.png!
70
71 25 Frédéric Blanc
connect
72
73 28 Frédéric Blanc
!clipboard-202304261515-hhbvn.png!
74 25 Frédéric Blanc
75 24 Frédéric Blanc
From the menu click on Validate Design
76
77
In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper'
78
79 26 Frédéric Blanc
!clipboard-202304261503-3iuu2.png!
80
81 24 Frédéric Blanc
Proceed to run Synthesis, Implementation and Bitstream Generation
82
83
Find the bitstream file (you may use the command 'find . -name *bit')
84
85
Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit)
86
87 22 Frédéric Blanc
clic doit 
88 23 Frédéric Blanc
!clipboard-202304261446-zpxnx.png!
89 22 Frédéric Blanc
90 10 Frédéric Blanc
Tcl Console
91
92 9 Frédéric Blanc
<pre><code class="shell">
93
cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink
94
source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl
95
</code></pre>
96
97 11 Frédéric Blanc
!clipboard-202304251008-te1ah.png!
98 17 Frédéric Blanc
pour éviter cette erreur copier le dossier core dans ../tmp/
99 11 Frédéric Blanc
100 16 Frédéric Blanc
attachment:cores.zip
101 12 Frédéric Blanc
102 18 Frédéric Blanc
h4. Bitstream
103
104 43 Frédéric Blanc
le Bitstream ce trouve dans le dossier /.../RedPitaya/fpga/<project...>/<project...>.runs/impl_1
105
106 18 Frédéric Blanc
!clipboard-202304251107-19zhk.png!
107
108 20 Frédéric Blanc
109
le fichier bitstream doit être remplacer le fichier /dev/xdevcfg
110
111 44 Frédéric Blanc
112
*rp-ip 140.93.64.197*
113
114
Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit)
115
116
Connect to the RedPitaya (ssh root@rp-ip)
117
118
Program the FPGA with the command cat file_name.bit > /dev/xdevcfg
119
120 45 Frédéric Blanc
h3. Console TCL
121 44 Frédéric Blanc
122 45 Frédéric Blanc
utilisation des exemples 
123
124
https://github.com/RedPitaya/RedPitaya-FPGA
125
126
!clipboard-202306021352-vc13m.png!
127
128
utiliser les commandes suivante dans vivado console TCL
129
130
<pre><code class="shell">
131
cd /tools/redpitaya/RedPitaya-FPGA-master/prj/Examples
132
source make_project.tcl
133
</code></pre>
134 46 Frédéric Blanc
cela va ouvrir le projet complet de Led_Blink
135
136 1 Frédéric Blanc
h3. tuto Web
137 19 Frédéric Blanc
138 21 Frédéric Blanc
https://github.com/lvillasen/RedPitaya-Hello-World
139
140 19 Frédéric Blanc
https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html
141 7 Frédéric Blanc
142
https://antonpotocnik.com/?p=487360
143 29 Frédéric Blanc
144
https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf
145 30 Frédéric Blanc
146
http://jmfriedt.free.fr/redpitaya.pdf
147 31 Frédéric Blanc
148
http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf