Xilink Vivado » History » Version 55
Frédéric Blanc, 2023-06-15 09:46
1 | 1 | Frédéric Blanc | h1. Xilink Vivado |
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3 | h2. installation Ubuntu 20.04 |
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4 | 33 | Frédéric Blanc | |
5 | sur le site de xilinx telecharger: |
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6 | https://www.xilinx.com/support/download.html |
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7 | 35 | Frédéric Blanc | Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer |
8 | 33 | Frédéric Blanc | |
9 | 37 | Frédéric Blanc | |
10 | 34 | Frédéric Blanc | *en root* |
11 | 33 | Frédéric Blanc | |
12 | 1 | Frédéric Blanc | <pre><code class="shell"> |
13 | 42 | Frédéric Blanc | sudo bash |
14 | 40 | Frédéric Blanc | export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr |
15 | 39 | Frédéric Blanc | chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
16 | 36 | Frédéric Blanc | sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
17 | 33 | Frédéric Blanc | </code></pre> |
18 | 41 | Frédéric Blanc | echo $XILINXD_LICENSE_FILE |
19 | 2100@flexalter.laas.fr |
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20 | 33 | Frédéric Blanc | |
21 | 32 | Frédéric Blanc | |
22 | https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/ |
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23 | |||
24 | 1 | Frédéric Blanc | h2. installation Windows |
25 | |||
26 | 6 | Frédéric Blanc | |
27 | 5 | Frédéric Blanc | h3. Vivado 2022.2 |
28 | |||
29 | 2 | Frédéric Blanc | Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory |
30 | |||
31 | On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. |
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32 | 3 | Frédéric Blanc | |
33 | <pre><code class="shell"> |
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34 | dir D:\Public\RedPitaya-FPGA |
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35 | vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 |
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36 | </code></pre> |
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37 | 4 | Frédéric Blanc | |
38 | !clipboard-202304201305-exdsl.png! |
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39 | 5 | Frédéric Blanc | |
40 | We recommend Vivado 2020.1 |
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41 | 7 | Frédéric Blanc | |
42 | 8 | Frédéric Blanc | h3. Vivado 2020.1 |
43 | 7 | Frédéric Blanc | |
44 | 22 | Frédéric Blanc | h2. Création d'un nouveau projet |
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46 | 47 | Frédéric Blanc | Create a new project with Vivado. |
47 | !clipboard-202306070934-1ikrj.png! |
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48 | |||
49 | Select the device xc7z010clg400-1 |
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50 | |||
51 | Add the constraint redpitaya.xdc . |
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52 | |||
53 | Create a new Block Design |
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54 | !clipboard-202306070939-6delu.png! |
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55 | |||
56 | h3. source |
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57 | |||
58 | 24 | Frédéric Blanc | soource: https://github.com/lvillasen/RedPitaya-Hello-World |
59 | |||
60 | Clone the repositiry |
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61 | |||
62 | Create a new project with Vivado. |
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63 | 47 | Frédéric Blanc | !clipboard-202306070934-1ikrj.png! |
64 | 24 | Frédéric Blanc | |
65 | Select the device xc7z010clg400-1 |
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66 | 1 | Frédéric Blanc | |
67 | 47 | Frédéric Blanc | Add the constraint redpitaya.xdc . |
68 | 1 | Frédéric Blanc | |
69 | 47 | Frédéric Blanc | Create a new Block Design |
70 | !clipboard-202306070939-6delu.png! |
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71 | 24 | Frédéric Blanc | |
72 | Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options. |
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73 | |||
74 | Add Module counter.v from the menu. |
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75 | |||
76 | clic doit |
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77 | !clipboard-202304261446-zpxnx.png! |
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78 | |||
79 | Add a Binary Counter from thr Add IP menu. |
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80 | |||
81 | Add a port called led_o with components from 7 down to 0. |
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82 | |||
83 | !clipboard-202304261452-qlhno.png! |
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84 | |||
85 | 25 | Frédéric Blanc | connect |
86 | |||
87 | 28 | Frédéric Blanc | !clipboard-202304261515-hhbvn.png! |
88 | 25 | Frédéric Blanc | |
89 | 24 | Frédéric Blanc | From the menu click on Validate Design |
90 | |||
91 | In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper' |
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92 | |||
93 | 26 | Frédéric Blanc | !clipboard-202304261503-3iuu2.png! |
94 | |||
95 | 24 | Frédéric Blanc | Proceed to run Synthesis, Implementation and Bitstream Generation |
96 | |||
97 | Find the bitstream file (you may use the command 'find . -name *bit') |
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98 | |||
99 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
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100 | |||
101 | 22 | Frédéric Blanc | clic doit |
102 | 23 | Frédéric Blanc | !clipboard-202304261446-zpxnx.png! |
103 | 22 | Frédéric Blanc | |
104 | 10 | Frédéric Blanc | Tcl Console |
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106 | 9 | Frédéric Blanc | <pre><code class="shell"> |
107 | cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink |
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108 | source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl |
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109 | </code></pre> |
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110 | |||
111 | 11 | Frédéric Blanc | !clipboard-202304251008-te1ah.png! |
112 | 17 | Frédéric Blanc | pour éviter cette erreur copier le dossier core dans ../tmp/ |
113 | 11 | Frédéric Blanc | |
114 | 16 | Frédéric Blanc | attachment:cores.zip |
115 | 12 | Frédéric Blanc | |
116 | 18 | Frédéric Blanc | h4. Bitstream |
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118 | 43 | Frédéric Blanc | le Bitstream ce trouve dans le dossier /.../RedPitaya/fpga/<project...>/<project...>.runs/impl_1 |
119 | |||
120 | 18 | Frédéric Blanc | !clipboard-202304251107-19zhk.png! |
121 | |||
122 | 20 | Frédéric Blanc | |
123 | le fichier bitstream doit être remplacer le fichier /dev/xdevcfg |
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124 | |||
125 | 44 | Frédéric Blanc | |
126 | *rp-ip 140.93.64.197* |
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127 | |||
128 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
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129 | |||
130 | Connect to the RedPitaya (ssh root@rp-ip) |
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131 | |||
132 | Program the FPGA with the command cat file_name.bit > /dev/xdevcfg |
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133 | |||
134 | 45 | Frédéric Blanc | h3. Console TCL |
135 | 44 | Frédéric Blanc | |
136 | 45 | Frédéric Blanc | utilisation des exemples |
137 | |||
138 | https://github.com/RedPitaya/RedPitaya-FPGA |
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139 | |||
140 | !clipboard-202306021352-vc13m.png! |
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141 | |||
142 | utiliser les commandes suivante dans vivado console TCL |
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143 | |||
144 | <pre><code class="shell"> |
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145 | cd /tools/redpitaya/RedPitaya-FPGA-master/prj/Examples |
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146 | source make_project.tcl |
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147 | </code></pre> |
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148 | 46 | Frédéric Blanc | cela va ouvrir le projet complet de Led_Blink |
149 | |||
150 | 48 | Frédéric Blanc | h3. GPIO |
151 | |||
152 | 50 | Frédéric Blanc | !clipboard-202306071537-n2vfw.png! |
153 | 49 | Frédéric Blanc | connecteur E1 |
154 | exp_n_tri_io |
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155 | exp_p_tri_io |
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156 | 51 | Frédéric Blanc | |
157 | 52 | Frédéric Blanc | exp_n_tri_io[1.1] correspond a DIO1_N |
158 | 53 | Frédéric Blanc | !clipboard-202306081407-xqky7.png! |
159 | !clipboard-202306081409-vulz6.png! |
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160 | 54 | Frédéric Blanc | exemple de slice pour extraire du vecteur exp_p_tri_io[7.0] le scalaire exp_p_tri_io[3.3] qui correspond au GPIO DIO3_P du connecteur E1 |
161 | 53 | Frédéric Blanc | Slice pour démultiplexer le vecteur |
162 | Concat pour multiplexer |
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163 | 48 | Frédéric Blanc | |
164 | 55 | Frédéric Blanc | h3. FIFO |
165 | |||
166 | !clipboard-202306150945-ewnfh.png! |
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167 | IP FIFO generator |
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168 | |||
169 | 1 | Frédéric Blanc | h3. tuto Web |
170 | 19 | Frédéric Blanc | |
171 | 21 | Frédéric Blanc | https://github.com/lvillasen/RedPitaya-Hello-World |
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173 | 19 | Frédéric Blanc | https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html |
174 | 7 | Frédéric Blanc | |
175 | https://antonpotocnik.com/?p=487360 |
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176 | 29 | Frédéric Blanc | |
177 | https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf |
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178 | 30 | Frédéric Blanc | |
179 | http://jmfriedt.free.fr/redpitaya.pdf |
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180 | 31 | Frédéric Blanc | |
181 | http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf |