Xilink Vivado » History » Version 70
Frédéric Blanc, 2023-10-23 15:32
1 | 1 | Frédéric Blanc | h1. Xilink Vivado |
---|---|---|---|
2 | |||
3 | h2. installation Ubuntu 20.04 |
||
4 | 33 | Frédéric Blanc | |
5 | sur le site de xilinx telecharger: |
||
6 | https://www.xilinx.com/support/download.html |
||
7 | 35 | Frédéric Blanc | Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer |
8 | 33 | Frédéric Blanc | |
9 | 37 | Frédéric Blanc | |
10 | 34 | Frédéric Blanc | *en root* |
11 | 33 | Frédéric Blanc | |
12 | 1 | Frédéric Blanc | <pre><code class="shell"> |
13 | 42 | Frédéric Blanc | sudo bash |
14 | 40 | Frédéric Blanc | export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr |
15 | 39 | Frédéric Blanc | chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
16 | 36 | Frédéric Blanc | sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
17 | 33 | Frédéric Blanc | </code></pre> |
18 | 41 | Frédéric Blanc | echo $XILINXD_LICENSE_FILE |
19 | 2100@flexalter.laas.fr |
||
20 | 33 | Frédéric Blanc | |
21 | 32 | Frédéric Blanc | |
22 | https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/ |
||
23 | |||
24 | 1 | Frédéric Blanc | h2. installation Windows |
25 | |||
26 | 6 | Frédéric Blanc | |
27 | 5 | Frédéric Blanc | h3. Vivado 2022.2 |
28 | |||
29 | 2 | Frédéric Blanc | Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory |
30 | |||
31 | On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. |
||
32 | 3 | Frédéric Blanc | |
33 | <pre><code class="shell"> |
||
34 | dir D:\Public\RedPitaya-FPGA |
||
35 | vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 |
||
36 | </code></pre> |
||
37 | 4 | Frédéric Blanc | |
38 | !clipboard-202304201305-exdsl.png! |
||
39 | 5 | Frédéric Blanc | |
40 | We recommend Vivado 2020.1 |
||
41 | 7 | Frédéric Blanc | |
42 | 8 | Frédéric Blanc | h3. Vivado 2020.1 |
43 | 7 | Frédéric Blanc | |
44 | 22 | Frédéric Blanc | h2. Création d'un nouveau projet |
45 | |||
46 | 47 | Frédéric Blanc | Create a new project with Vivado. |
47 | !clipboard-202306070934-1ikrj.png! |
||
48 | |||
49 | 67 | Frédéric Blanc | *Select the device xc7z010clg400-1* |
50 | 47 | Frédéric Blanc | |
51 | Add the constraint redpitaya.xdc . |
||
52 | |||
53 | Create a new Block Design |
||
54 | !clipboard-202306070939-6delu.png! |
||
55 | |||
56 | 57 | Frédéric Blanc | *ERROR: Could not find a top module* |
57 | |||
58 | solution Create an HDL Wrapper. |
||
59 | !clipboard-202306201313-n0s0q.png! |
||
60 | |||
61 | 47 | Frédéric Blanc | h3. source |
62 | |||
63 | 24 | Frédéric Blanc | soource: https://github.com/lvillasen/RedPitaya-Hello-World |
64 | |||
65 | Clone the repositiry |
||
66 | |||
67 | Create a new project with Vivado. |
||
68 | 47 | Frédéric Blanc | !clipboard-202306070934-1ikrj.png! |
69 | 24 | Frédéric Blanc | |
70 | 66 | Frédéric Blanc | *Select the device xc7z010clg400-1* |
71 | 1 | Frédéric Blanc | |
72 | 47 | Frédéric Blanc | Add the constraint redpitaya.xdc . |
73 | 1 | Frédéric Blanc | |
74 | 47 | Frédéric Blanc | Create a new Block Design |
75 | !clipboard-202306070939-6delu.png! |
||
76 | 24 | Frédéric Blanc | |
77 | Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options. |
||
78 | |||
79 | Add Module counter.v from the menu. |
||
80 | |||
81 | clic doit |
||
82 | !clipboard-202304261446-zpxnx.png! |
||
83 | |||
84 | Add a Binary Counter from thr Add IP menu. |
||
85 | |||
86 | Add a port called led_o with components from 7 down to 0. |
||
87 | |||
88 | !clipboard-202304261452-qlhno.png! |
||
89 | |||
90 | 25 | Frédéric Blanc | connect |
91 | |||
92 | 28 | Frédéric Blanc | !clipboard-202304261515-hhbvn.png! |
93 | 25 | Frédéric Blanc | |
94 | 24 | Frédéric Blanc | From the menu click on Validate Design |
95 | |||
96 | In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper' |
||
97 | |||
98 | 26 | Frédéric Blanc | !clipboard-202304261503-3iuu2.png! |
99 | |||
100 | 24 | Frédéric Blanc | Proceed to run Synthesis, Implementation and Bitstream Generation |
101 | |||
102 | Find the bitstream file (you may use the command 'find . -name *bit') |
||
103 | |||
104 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
||
105 | |||
106 | 22 | Frédéric Blanc | clic doit |
107 | 23 | Frédéric Blanc | !clipboard-202304261446-zpxnx.png! |
108 | 22 | Frédéric Blanc | |
109 | 10 | Frédéric Blanc | Tcl Console |
110 | |||
111 | 9 | Frédéric Blanc | <pre><code class="shell"> |
112 | cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink |
||
113 | source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl |
||
114 | </code></pre> |
||
115 | |||
116 | 11 | Frédéric Blanc | !clipboard-202304251008-te1ah.png! |
117 | 17 | Frédéric Blanc | pour éviter cette erreur copier le dossier core dans ../tmp/ |
118 | 11 | Frédéric Blanc | |
119 | 16 | Frédéric Blanc | attachment:cores.zip |
120 | 12 | Frédéric Blanc | |
121 | 18 | Frédéric Blanc | h4. Bitstream |
122 | |||
123 | 43 | Frédéric Blanc | le Bitstream ce trouve dans le dossier /.../RedPitaya/fpga/<project...>/<project...>.runs/impl_1 |
124 | |||
125 | 18 | Frédéric Blanc | !clipboard-202304251107-19zhk.png! |
126 | |||
127 | 20 | Frédéric Blanc | |
128 | le fichier bitstream doit être remplacer le fichier /dev/xdevcfg |
||
129 | |||
130 | 44 | Frédéric Blanc | |
131 | *rp-ip 140.93.64.197* |
||
132 | |||
133 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
||
134 | |||
135 | Connect to the RedPitaya (ssh root@rp-ip) |
||
136 | |||
137 | Program the FPGA with the command cat file_name.bit > /dev/xdevcfg |
||
138 | |||
139 | 69 | Frédéric Blanc | h2. GPIO |
140 | |||
141 | |||
142 | 45 | Frédéric Blanc | h3. Console TCL |
143 | 44 | Frédéric Blanc | |
144 | 45 | Frédéric Blanc | utilisation des exemples |
145 | |||
146 | https://github.com/RedPitaya/RedPitaya-FPGA |
||
147 | |||
148 | !clipboard-202306021352-vc13m.png! |
||
149 | |||
150 | utiliser les commandes suivante dans vivado console TCL |
||
151 | |||
152 | <pre><code class="shell"> |
||
153 | cd /tools/redpitaya/RedPitaya-FPGA-master/prj/Examples |
||
154 | source make_project.tcl |
||
155 | </code></pre> |
||
156 | 46 | Frédéric Blanc | cela va ouvrir le projet complet de Led_Blink |
157 | |||
158 | 48 | Frédéric Blanc | h3. GPIO |
159 | |||
160 | 50 | Frédéric Blanc | !clipboard-202306071537-n2vfw.png! |
161 | 49 | Frédéric Blanc | connecteur E1 |
162 | 65 | Frédéric Blanc | exp_n_tri_io (OUT) |
163 | exp_p_tri_io (IN) |
||
164 | 51 | Frédéric Blanc | |
165 | 52 | Frédéric Blanc | exp_n_tri_io[1.1] correspond a DIO1_N |
166 | 53 | Frédéric Blanc | !clipboard-202306081407-xqky7.png! |
167 | !clipboard-202306081409-vulz6.png! |
||
168 | 54 | Frédéric Blanc | exemple de slice pour extraire du vecteur exp_p_tri_io[7.0] le scalaire exp_p_tri_io[3.3] qui correspond au GPIO DIO3_P du connecteur E1 |
169 | 53 | Frédéric Blanc | Slice pour démultiplexer le vecteur |
170 | Concat pour multiplexer |
||
171 | 48 | Frédéric Blanc | |
172 | 70 | Frédéric Blanc | h4. bidirectional |
173 | |||
174 | IOBUF |
||
175 | |||
176 | !clipboard-202310231532-idfoo.png! |
||
177 | |||
178 | https://docs.xilinx.com/r/en-US/ug1344-versal-architecture-libraries/IBUFDS_DIFF_OUT_IBUFDISABLE |
||
179 | |||
180 | 55 | Frédéric Blanc | h3. FIFO |
181 | |||
182 | 59 | Frédéric Blanc | !clipboard-202306221115-rthjy.png! |
183 | 55 | Frédéric Blanc | IP FIFO generator |
184 | 58 | Frédéric Blanc | *IN* |
185 | 1 | Frédéric Blanc | !clipboard-202306151112-equbx.png! |
186 | 58 | Frédéric Blanc | *OUT* |
187 | 56 | Frédéric Blanc | !clipboard-202306151112-gvamj.png! |
188 | |||
189 | 62 | Frédéric Blanc | h3. Shift Register |
190 | |||
191 | !clipboard-202307041436-0ex9q.png! |
||
192 | |||
193 | 63 | Frédéric Blanc | h3. Block Memory Generator |
194 | |||
195 | !clipboard-202307041437-3fhkj.png! |
||
196 | |||
197 | 68 | Frédéric Blanc | h3. test clock |
198 | |||
199 | !clipboard-202309071030-znwjj.png! |
||
200 | clk_463157890Hz |
||
201 | |||
202 | 1 | Frédéric Blanc | h3. tuto Web |
203 | 19 | Frédéric Blanc | |
204 | 21 | Frédéric Blanc | https://github.com/lvillasen/RedPitaya-Hello-World |
205 | |||
206 | 19 | Frédéric Blanc | https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html |
207 | 7 | Frédéric Blanc | |
208 | https://antonpotocnik.com/?p=487360 |
||
209 | 29 | Frédéric Blanc | |
210 | https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf |
||
211 | 30 | Frédéric Blanc | |
212 | http://jmfriedt.free.fr/redpitaya.pdf |
||
213 | 31 | Frédéric Blanc | |
214 | http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf |
||
215 | 60 | Frédéric Blanc | |
216 | RAM |
||
217 | |||
218 | https://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynq |
||
219 | 61 | Frédéric Blanc | |
220 | 1 | Frédéric Blanc | https://elinux.org/Connect_a_ARM_Microcontroller_to_a_FPGA_using_its_Extended_Memory_Interface_%28EMI%29 |
221 | 64 | Frédéric Blanc | |
222 | http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorial.pdf |