Frédéric Blanc » Red Pitaya

h1. Xilink Vivado

h2. installation Ubuntu 20.04

sur le site de xilinx telecharger:

https://www.xilinx.com/support/download.html

Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer

*en root*

<pre><code class="shell">

sudo bash

export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr

chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin

sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin

</code></pre>

echo $XILINXD_LICENSE_FILE

2100@flexalter.laas.fr

https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/

h2. installation Windows

h3. Vivado 2022.2

Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory

On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell.

<pre><code class="shell">

dir D:\Public\RedPitaya-FPGA

vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94

</code></pre>

!clipboard-202304201305-exdsl.png!

We recommend Vivado 2020.1

h3. Vivado 2020.1

h2. Création d'un nouveau projet

Create a new project with Vivado.

!clipboard-202306070934-1ikrj.png!

*Select the device xc7z010clg400-1*

Add the constraint redpitaya.xdc .

Create a new Block Design 

!clipboard-202306070939-6delu.png!

*ERROR: Could not find a top module*

solution Create an HDL Wrapper.

!clipboard-202306201313-n0s0q.png!

h3. source 

soource: https://github.com/lvillasen/RedPitaya-Hello-World

Clone the repositiry

Create a new project with Vivado.

!clipboard-202306070934-1ikrj.png!

*Select the device xc7z010clg400-1*

Add the constraint redpitaya.xdc .

Create a new Block Design 

!clipboard-202306070939-6delu.png!

Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options.

Add Module counter.v from the menu.

clic doit 

!clipboard-202304261446-zpxnx.png!

Add a Binary Counter from thr Add IP menu.

Add a port called led_o with components from 7 down to 0.

!clipboard-202304261452-qlhno.png!

connect

!clipboard-202304261515-hhbvn.png!

From the menu click on Validate Design

In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper'

!clipboard-202304261503-3iuu2.png!

Proceed to run Synthesis, Implementation and Bitstream Generation

Find the bitstream file (you may use the command 'find . -name *bit')

Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit)

clic doit 

!clipboard-202304261446-zpxnx.png!

Tcl Console

<pre><code class="shell">

cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink

source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl

</code></pre>

!clipboard-202304251008-te1ah.png!

pour éviter cette erreur copier le dossier core dans ../tmp/

attachment:cores.zip

h4. Bitstream

le Bitstream ce trouve dans le dossier /.../RedPitaya/fpga/<project...>/<project...>.runs/impl_1

!clipboard-202304251107-19zhk.png!

le fichier bitstream doit être remplacer le fichier /dev/xdevcfg

*rp-ip 140.93.64.197*

Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit)

Connect to the RedPitaya (ssh root@rp-ip)

Program the FPGA with the command cat file_name.bit > /dev/xdevcfg

h2. GPIO

h3. Console TCL

utilisation des exemples 

https://github.com/RedPitaya/RedPitaya-FPGA

!clipboard-202306021352-vc13m.png!

utiliser les commandes suivante dans vivado console TCL

<pre><code class="shell">

cd /tools/redpitaya/RedPitaya-FPGA-master/prj/Examples

source make_project.tcl

</code></pre>

cela va ouvrir le projet complet de Led_Blink

h3. GPIO

!clipboard-202306071537-n2vfw.png!

connecteur E1

exp_n_tri_io    (OUT)

exp_p_tri_io    (IN)

exp_n_tri_io[1.1] correspond a DIO1_N

!clipboard-202306081407-xqky7.png!

!clipboard-202306081409-vulz6.png!

exemple de slice pour extraire du vecteur exp_p_tri_io[7.0] le scalaire exp_p_tri_io[3.3] qui correspond au GPIO DIO3_P du connecteur E1

Slice pour démultiplexer le vecteur

Concat pour multiplexer

h4. bidirectional

h5. IOBUF

!clipboard-202310231532-idfoo.png!

https://docs.xilinx.com/r/en-US/ug1344-versal-architecture-libraries/IBUFDS_DIFF_OUT_IBUFDISABLE

h5. Utility Buffer (seulement pour les horloges)

https://www.xilinx.com/products/intellectual-property/util_ds_buf.html#documentation

h5. Modification du fichier de contraite

<pre><code class="shell">

### set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]

set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]

 ### IN

 set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_in7[*]}]

 set_property SLEW FAST [get_ports {exp_p_in7[*]}]

 set_property DRIVE 8 [get_ports {exp_p_in7[*]}]

 set_property PULLTYPE PULLUP [get_ports {exp_p_in7[*]}]

 set_property PACKAGE_PIN M14 [get_ports {exp_p_in7[0]}]

</code></pre>

h3. FIFO

!clipboard-202306221115-rthjy.png!

IP FIFO generator

*IN*

!clipboard-202306151112-equbx.png!

*OUT*

!clipboard-202306151112-gvamj.png!

h3. Shift Register

!clipboard-202307041436-0ex9q.png!

h3. Block Memory Generator

!clipboard-202307041437-3fhkj.png!

h3. Clock

le mode auto ne détecte pas le 125MHz(FCLK_CLK0) mais semble prendre 50MHz, d'ou une erreur de x2.5 (overcloking)

!clipboard-202310301446-afoxm.png!

parametre a modifier dans le zynq pour avoir la bonne fréquence 125MHz(FCLK_CLK0) 

!clipboard-202310301443-qm7dq.png!

h3. Bascule D flip-flop

!clipboard-202310301320-froal.png!

util ff

h3. PULSE

!clipboard-202310301452-mrz0e.png!

bascule D en mode FDCE, wizard clock 400Mhz bus par défaul 50Mhz (125MHz réel)

h2. RAM

!clipboard-202311061559-umyvt.png!

https://forum.redpitaya.com/viewtopic.php?t=1675

https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html/

How to control AXI DMA and/or BRAM cores in a ZYNQ

https://electronics.stackexchange.com/questions/482233/how-to-control-axi-dma-and-or-bram-cores-in-a-zynq

h3. tuto Web

https://github.com/lvillasen/RedPitaya-Hello-World

https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html

https://antonpotocnik.com/?p=487360

https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf

http://jmfriedt.free.fr/redpitaya.pdf

http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf

RAM

https://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynq

https://elinux.org/Connect_a_ARM_Microcontroller_to_a_FPGA_using_its_Extended_Memory_Interface_%28EMI%29

http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorial.pdf

https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html/