Xilink Vivado » History » Version 91
Frédéric Blanc, 2023-12-07 10:04
1 | 1 | Frédéric Blanc | h1. Xilink Vivado |
---|---|---|---|
2 | 90 | Frédéric Blanc | |
3 | 89 | Frédéric Blanc | {{toc}} |
4 | 90 | Frédéric Blanc | |
5 | 91 | Frédéric Blanc | WIKI principal [[Wiki]] |
6 | |||
7 | 1 | Frédéric Blanc | h2. installation Ubuntu 20.04 |
8 | 33 | Frédéric Blanc | |
9 | sur le site de xilinx telecharger: |
||
10 | https://www.xilinx.com/support/download.html |
||
11 | 35 | Frédéric Blanc | Xilinx Unified Installer 2020.1: Linux Self Extracting Web Installer |
12 | 33 | Frédéric Blanc | |
13 | 37 | Frédéric Blanc | |
14 | 34 | Frédéric Blanc | *en root* |
15 | 33 | Frédéric Blanc | |
16 | 1 | Frédéric Blanc | <pre><code class="shell"> |
17 | 42 | Frédéric Blanc | sudo bash |
18 | 40 | Frédéric Blanc | export XILINXD_LICENSE_FILE=2100@flexalter.laas.fr |
19 | 39 | Frédéric Blanc | chmod +x Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
20 | 36 | Frédéric Blanc | sudo ./Xilinx_Unified_2020.1_0602_1208_Lin64.bin |
21 | 33 | Frédéric Blanc | </code></pre> |
22 | 41 | Frédéric Blanc | echo $XILINXD_LICENSE_FILE |
23 | 2100@flexalter.laas.fr |
||
24 | 33 | Frédéric Blanc | |
25 | 32 | Frédéric Blanc | |
26 | https://danielmangum.com/posts/vivado-2020-x-ubuntu-20-04/ |
||
27 | |||
28 | 1 | Frédéric Blanc | h2. installation Windows |
29 | |||
30 | 6 | Frédéric Blanc | |
31 | 5 | Frédéric Blanc | h3. Vivado 2022.2 |
32 | |||
33 | 2 | Frédéric Blanc | Windows 64-bit: Run the settings64.bat from the Vivado/<version> directory |
34 | |||
35 | On Windows, click Start > All Programs > Xilinx Design Tools > Vivado 2022.2 > Vivado 2022.2 Tcl Shell to launch the Vivado Design Suite Tcl shell. |
||
36 | 3 | Frédéric Blanc | |
37 | <pre><code class="shell"> |
||
38 | dir D:\Public\RedPitaya-FPGA |
||
39 | vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 |
||
40 | </code></pre> |
||
41 | 4 | Frédéric Blanc | |
42 | !clipboard-202304201305-exdsl.png! |
||
43 | 5 | Frédéric Blanc | |
44 | We recommend Vivado 2020.1 |
||
45 | 7 | Frédéric Blanc | |
46 | 8 | Frédéric Blanc | h3. Vivado 2020.1 |
47 | 7 | Frédéric Blanc | |
48 | 22 | Frédéric Blanc | h2. Création d'un nouveau projet |
49 | |||
50 | 47 | Frédéric Blanc | Create a new project with Vivado. |
51 | !clipboard-202306070934-1ikrj.png! |
||
52 | |||
53 | 67 | Frédéric Blanc | *Select the device xc7z010clg400-1* |
54 | 47 | Frédéric Blanc | |
55 | Add the constraint redpitaya.xdc . |
||
56 | |||
57 | Create a new Block Design |
||
58 | !clipboard-202306070939-6delu.png! |
||
59 | |||
60 | 57 | Frédéric Blanc | *ERROR: Could not find a top module* |
61 | |||
62 | solution Create an HDL Wrapper. |
||
63 | !clipboard-202306201313-n0s0q.png! |
||
64 | |||
65 | 47 | Frédéric Blanc | h3. source |
66 | |||
67 | 86 | Frédéric Blanc | source: https://github.com/lvillasen/RedPitaya-Hello-World |
68 | 24 | Frédéric Blanc | |
69 | Clone the repositiry |
||
70 | |||
71 | Create a new project with Vivado. |
||
72 | 47 | Frédéric Blanc | !clipboard-202306070934-1ikrj.png! |
73 | 24 | Frédéric Blanc | |
74 | 66 | Frédéric Blanc | *Select the device xc7z010clg400-1* |
75 | 1 | Frédéric Blanc | |
76 | 47 | Frédéric Blanc | Add the constraint redpitaya.xdc . |
77 | 1 | Frédéric Blanc | |
78 | 47 | Frédéric Blanc | Create a new Block Design |
79 | !clipboard-202306070939-6delu.png! |
||
80 | 24 | Frédéric Blanc | |
81 | Add the IP called ZYNQ7 Processing System from the menu and Run Block Automation with default options. |
||
82 | |||
83 | Add Module counter.v from the menu. |
||
84 | |||
85 | clic doit |
||
86 | !clipboard-202304261446-zpxnx.png! |
||
87 | |||
88 | Add a Binary Counter from thr Add IP menu. |
||
89 | |||
90 | Add a port called led_o with components from 7 down to 0. |
||
91 | |||
92 | !clipboard-202304261452-qlhno.png! |
||
93 | |||
94 | 25 | Frédéric Blanc | connect |
95 | |||
96 | 28 | Frédéric Blanc | !clipboard-202304261515-hhbvn.png! |
97 | 25 | Frédéric Blanc | |
98 | 24 | Frédéric Blanc | From the menu click on Validate Design |
99 | |||
100 | In 'Sources' go to 'IP Sources' right-click on 'project1' and select 'Create HDL Wraper' |
||
101 | |||
102 | 26 | Frédéric Blanc | !clipboard-202304261503-3iuu2.png! |
103 | |||
104 | 24 | Frédéric Blanc | Proceed to run Synthesis, Implementation and Bitstream Generation |
105 | |||
106 | Find the bitstream file (you may use the command 'find . -name *bit') |
||
107 | |||
108 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
||
109 | |||
110 | 22 | Frédéric Blanc | clic doit |
111 | 23 | Frédéric Blanc | !clipboard-202304261446-zpxnx.png! |
112 | 22 | Frédéric Blanc | |
113 | 10 | Frédéric Blanc | Tcl Console |
114 | |||
115 | 9 | Frédéric Blanc | <pre><code class="shell"> |
116 | cd d:/Public/RedPitaya-FPGA/prj/Examples/Led_blink |
||
117 | source D:/Public/RedPitaya-FPGA/prj/Examples/Led_blink/make_project.tcl |
||
118 | </code></pre> |
||
119 | |||
120 | 11 | Frédéric Blanc | !clipboard-202304251008-te1ah.png! |
121 | 17 | Frédéric Blanc | pour éviter cette erreur copier le dossier core dans ../tmp/ |
122 | 11 | Frédéric Blanc | |
123 | 16 | Frédéric Blanc | attachment:cores.zip |
124 | 12 | Frédéric Blanc | |
125 | 18 | Frédéric Blanc | h4. Bitstream |
126 | |||
127 | 43 | Frédéric Blanc | le Bitstream ce trouve dans le dossier /.../RedPitaya/fpga/<project...>/<project...>.runs/impl_1 |
128 | |||
129 | 18 | Frédéric Blanc | !clipboard-202304251107-19zhk.png! |
130 | |||
131 | 20 | Frédéric Blanc | |
132 | le fichier bitstream doit être remplacer le fichier /dev/xdevcfg |
||
133 | |||
134 | 44 | Frédéric Blanc | |
135 | *rp-ip 140.93.64.197* |
||
136 | |||
137 | Transfer the bitstream file (*.bit) to the Red Pitaya (you may use *sftp root@rp-ip and put *.bit) |
||
138 | |||
139 | Connect to the RedPitaya (ssh root@rp-ip) |
||
140 | |||
141 | 88 | Frédéric Blanc | Program the FPGA with the command: |
142 | *cat file_name.bit > /dev/xdevcfg* |
||
143 | 44 | Frédéric Blanc | |
144 | 69 | Frédéric Blanc | h2. GPIO |
145 | |||
146 | |||
147 | 45 | Frédéric Blanc | h3. Console TCL |
148 | 44 | Frédéric Blanc | |
149 | 45 | Frédéric Blanc | utilisation des exemples |
150 | |||
151 | https://github.com/RedPitaya/RedPitaya-FPGA |
||
152 | |||
153 | !clipboard-202306021352-vc13m.png! |
||
154 | |||
155 | utiliser les commandes suivante dans vivado console TCL |
||
156 | |||
157 | <pre><code class="shell"> |
||
158 | cd /tools/redpitaya/RedPitaya-FPGA-master/prj/Examples |
||
159 | source make_project.tcl |
||
160 | </code></pre> |
||
161 | 46 | Frédéric Blanc | cela va ouvrir le projet complet de Led_Blink |
162 | |||
163 | 48 | Frédéric Blanc | h3. GPIO |
164 | |||
165 | 50 | Frédéric Blanc | !clipboard-202306071537-n2vfw.png! |
166 | 49 | Frédéric Blanc | connecteur E1 |
167 | 65 | Frédéric Blanc | exp_n_tri_io (OUT) |
168 | exp_p_tri_io (IN) |
||
169 | 51 | Frédéric Blanc | |
170 | 52 | Frédéric Blanc | exp_n_tri_io[1.1] correspond a DIO1_N |
171 | 53 | Frédéric Blanc | !clipboard-202306081407-xqky7.png! |
172 | !clipboard-202306081409-vulz6.png! |
||
173 | 54 | Frédéric Blanc | exemple de slice pour extraire du vecteur exp_p_tri_io[7.0] le scalaire exp_p_tri_io[3.3] qui correspond au GPIO DIO3_P du connecteur E1 |
174 | 53 | Frédéric Blanc | Slice pour démultiplexer le vecteur |
175 | Concat pour multiplexer |
||
176 | 48 | Frédéric Blanc | |
177 | 70 | Frédéric Blanc | h4. bidirectional |
178 | |||
179 | 72 | Frédéric Blanc | h5. IOBUF |
180 | 70 | Frédéric Blanc | |
181 | !clipboard-202310231532-idfoo.png! |
||
182 | |||
183 | https://docs.xilinx.com/r/en-US/ug1344-versal-architecture-libraries/IBUFDS_DIFF_OUT_IBUFDISABLE |
||
184 | |||
185 | 72 | Frédéric Blanc | h5. Utility Buffer (seulement pour les horloges) |
186 | 1 | Frédéric Blanc | |
187 | https://www.xilinx.com/products/intellectual-property/util_ds_buf.html#documentation |
||
188 | 72 | Frédéric Blanc | |
189 | h5. Modification du fichier de contraite |
||
190 | 71 | Frédéric Blanc | |
191 | 73 | Frédéric Blanc | <pre><code class="shell"> |
192 | ### set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}] |
||
193 | set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}] |
||
194 | ### IN |
||
195 | set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_in7[*]}] |
||
196 | set_property SLEW FAST [get_ports {exp_p_in7[*]}] |
||
197 | set_property DRIVE 8 [get_ports {exp_p_in7[*]}] |
||
198 | set_property PULLTYPE PULLUP [get_ports {exp_p_in7[*]}] |
||
199 | set_property PACKAGE_PIN M14 [get_ports {exp_p_in7[0]}] |
||
200 | </code></pre> |
||
201 | |||
202 | |||
203 | |||
204 | 55 | Frédéric Blanc | h3. FIFO |
205 | |||
206 | 59 | Frédéric Blanc | !clipboard-202306221115-rthjy.png! |
207 | 55 | Frédéric Blanc | IP FIFO generator |
208 | 58 | Frédéric Blanc | *IN* |
209 | 1 | Frédéric Blanc | !clipboard-202306151112-equbx.png! |
210 | 58 | Frédéric Blanc | *OUT* |
211 | 56 | Frédéric Blanc | !clipboard-202306151112-gvamj.png! |
212 | |||
213 | 62 | Frédéric Blanc | h3. Shift Register |
214 | |||
215 | !clipboard-202307041436-0ex9q.png! |
||
216 | |||
217 | 63 | Frédéric Blanc | h3. Block Memory Generator |
218 | |||
219 | !clipboard-202307041437-3fhkj.png! |
||
220 | |||
221 | 75 | Frédéric Blanc | h3. Clock |
222 | 1 | Frédéric Blanc | |
223 | 76 | Frédéric Blanc | le mode auto ne détecte pas le 125MHz(FCLK_CLK0) mais semble prendre 50MHz, d'ou une erreur de x2.5 (overcloking) |
224 | 75 | Frédéric Blanc | !clipboard-202310301446-afoxm.png! |
225 | |||
226 | parametre a modifier dans le zynq pour avoir la bonne fréquence 125MHz(FCLK_CLK0) |
||
227 | |||
228 | !clipboard-202310301443-qm7dq.png! |
||
229 | 68 | Frédéric Blanc | |
230 | 74 | Frédéric Blanc | h3. Bascule D flip-flop |
231 | |||
232 | !clipboard-202310301320-froal.png! |
||
233 | util ff |
||
234 | |||
235 | 77 | Frédéric Blanc | h3. PULSE |
236 | |||
237 | !clipboard-202310301452-mrz0e.png! |
||
238 | 78 | Frédéric Blanc | bascule D en mode FDCE, wizard clock 400Mhz bus par défaul 50Mhz (125MHz réel) |
239 | 77 | Frédéric Blanc | |
240 | 79 | Frédéric Blanc | h2. RAM |
241 | |||
242 | 87 | Frédéric Blanc | |
243 | voir tuto document:"tuto vivado memoire partagé CPU-FPGA" |
||
244 | |||
245 | 82 | Frédéric Blanc | https://forum.redpitaya.com/viewtopic.php?t=1795 |
246 | |||
247 | 83 | Frédéric Blanc | !clipboard-202311070920-og7mi.png! |
248 | |||
249 | 81 | Frédéric Blanc | !clipboard-202311061559-umyvt.png! |
250 | |||
251 | 80 | Frédéric Blanc | https://forum.redpitaya.com/viewtopic.php?t=1675 |
252 | |||
253 | 79 | Frédéric Blanc | https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html/ |
254 | |||
255 | How to control AXI DMA and/or BRAM cores in a ZYNQ |
||
256 | |||
257 | https://electronics.stackexchange.com/questions/482233/how-to-control-axi-dma-and-or-bram-cores-in-a-zynq |
||
258 | |||
259 | 84 | Frédéric Blanc | tuto a verifier |
260 | https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/controlling-led-brightness-by-pwm-on-minized |
||
261 | |||
262 | 85 | Frédéric Blanc | https://community.element14.com/challenges-projects/design-challenges/pathtoprogrammable/b/blog/posts/path-to-programmable---lab-8---pwm-controller |
263 | |||
264 | 1 | Frédéric Blanc | h3. tuto Web |
265 | 19 | Frédéric Blanc | |
266 | 21 | Frédéric Blanc | https://github.com/lvillasen/RedPitaya-Hello-World |
267 | |||
268 | 19 | Frédéric Blanc | https://redpitaya.readthedocs.io/en/latest/developerGuide/software/build/fpga/fpga.html |
269 | 7 | Frédéric Blanc | |
270 | https://antonpotocnik.com/?p=487360 |
||
271 | 29 | Frédéric Blanc | |
272 | https://easytp.cnam.fr/alexandre/index_fichiers/support/zynq_cours_tp_vivado_zc702.pdf |
||
273 | 30 | Frédéric Blanc | |
274 | http://jmfriedt.free.fr/redpitaya.pdf |
||
275 | 31 | Frédéric Blanc | |
276 | http://staff.ltam.lu/feljc/electronics/redpitaya/RedPitayaScriptingSummary_1.pdf |
||
277 | 60 | Frédéric Blanc | |
278 | RAM |
||
279 | |||
280 | https://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynq |
||
281 | 61 | Frédéric Blanc | |
282 | 1 | Frédéric Blanc | https://elinux.org/Connect_a_ARM_Microcontroller_to_a_FPGA_using_its_Extended_Memory_Interface_%28EMI%29 |
283 | 64 | Frédéric Blanc | |
284 | http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorial.pdf |
||
285 | 79 | Frédéric Blanc | |
286 | https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html/ |