Shared RAM CPU FPGA » History » Version 10
Frédéric Blanc, 2023-12-07 13:40
| 1 | 1 | Frédéric Blanc | h1. Shared RAM CPU FPGA |
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| 3 | 9 | Frédéric Blanc | h2. Cache |
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| 5 | https://docs.xilinx.com/r/en-US/oslib_rm/Arm-Cortex-A53-64-bit-Processor-Cache-Functions |
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| 6 | 10 | Frédéric Blanc | https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexa9/xil_cache.h |
| 7 | 9 | Frédéric Blanc | |
| 8 | 1 | Frédéric Blanc | h2. Create Block |
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| 10 | !clipboard-202311131026-thzpz.png! |
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| 12 | 2 | Frédéric Blanc | h3. Configure BRAM |
| 13 | 1 | Frédéric Blanc | !clipboard-202311131035-htcja.png! |
| 14 | Memory Type: True Dual Port RAM |
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| 15 | !clipboard-202311131039-uqbax.png! |
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| 16 | (Disable) Enable Safety Circuit |
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| 17 | 2 | Frédéric Blanc | !clipboard-202311131043-wbbsw.png! |
| 18 | 3 | Frédéric Blanc | Run Connection Automation axi_gpio_0/S_AXI |
| 19 | 2 | Frédéric Blanc | !clipboard-202311131043-jszfx.png! |
| 20 | 1 | Frédéric Blanc | after Automation |
| 21 | 3 | Frédéric Blanc | |
| 22 | !clipboard-202311131045-aisy4.png! |
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| 23 | Run Connection Automation axi_gpio_0/gpio |
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| 24 | !clipboard-202311131047-kzdy7.png! |
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| 25 | After Automation |
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| 26 | |||
| 27 | !clipboard-202311131052-jlgz6.png! |
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| 28 | Run Connection Automation axi_gpio_0/gpio |
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| 29 | !clipboard-202311131051-p1my8.png! |
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| 30 | 4 | Frédéric Blanc | After Automation |
| 31 | |||
| 32 | !clipboard-202311131055-lg6tx.png! |
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| 33 | 5 | Frédéric Blanc | Address Editor |
| 34 | 6 | Frédéric Blanc | |
| 35 | h2. Ecriture dans la RAM |
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| 36 | |||
| 37 | Utilisation du programme : |
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| 38 | 7 | Frédéric Blanc | document:"memrw.c" |
| 39 | 8 | Frédéric Blanc | |
| 40 | 1 | Frédéric Blanc | h2. Source: |
| 41 | 8 | Frédéric Blanc | |
| 42 | 5 | Frédéric Blanc | https://support.xilinx.com/s/question/0D52E00006hplPeSAI/axi4-stream-fifo-keeps-data?language=en_US |
| 43 | 7 | Frédéric Blanc | https://forum.digilent.com/topic/3822-what-is-the-fastest-way-to-save-pl-data/ |